NVIDIA's Back with NV35 - GeForceFX 5900 Ultra

Stages 6 & 7: Raster Operations & DRAM accesses

The final stages in the 3D pipeline have been explained by us in the past on numerous occasions, so we will just touch on the enhancements as they apply to NV35.

First and foremost, NVIDIA's compression algorithms have been improved tremendously with the NV35 so that the biggest performance gains you will see will be in high resolution Anti-Aliasing modes; NVIDIA appropriately calls this their Intellisample High-resolution Compression Technology (HCT).

The next major improvement is the introduction of a 256-bit wide memory bus to the NV35. NVIDIA originally thought that BGA memory and flip-chip packaging technology would not be ready for prime time by NV30's introduction date and thus outfitted the original chip with no more than a 128-bit wide memory interface. The biggest challenges that exist with a 256-bit wide memory interface are routing related; routing traces to/from the GPU and to/from the individual memory chips themselves. Both flip chip packaging on the GPU side and BGA packaging on the memory side made a 256-bit memory interface an attainable reality, even on NV30.

Obviously with NV30 heavily delayed, NVIDIA didn't want to push things back even further to wait on a re-spin of the design with a wider memory bus, but with NV35 we finally have that 256-bit memory interface we've been craving.