SiS755 Reference Board: Athlon64 from SiS

SiS755 Reference Board: Stress Testing

We performed stress tests on the SiS755 Reference Board in these areas and configurations:

1. Chipset and motherboard stress testing, conducted by running the FSB at 215MHz.
2. Memory stress testing, conducted by running RAM at 400MHz with 2 DIMM slots filled and at 400MHz with all 3 DIMM slots filled at the lowest memory timings possible.

Front Side Bus Stress Test Results:

As normally done in our testing of production motherboards, we ran a full range of stress tests and benchmarks on the SiS755 Reference Board to test stability at an overclocked speed. This included Prime95 torture tests, and the addition of other tasks — data compression, various DX8 and DX9 games, and apps like Word and Excel — while Prime95 was running in the background. Finally, we ran our benchmark suite, which includes ZD Winstone suite, Unreal Tournament 2003, SPECviewperf 7.0, and Gun Metal Benchmark 2. At default voltage, 215MHz was the highest overclock that we were able to achieve with the SiS755 at 800 HT while running these tests.

Unlike our experiences with some of the VIA K8T800 overclock, the SiS was completely stable when it was able to run an overclock. The PCI/AGP lock, at the very least, appears to improve stability of the overclocked speed.

Memory Stress Test Results:

This memory stress test simply tests the ability of the SiS755 Reference Board to operate at its officially supported memory frequency (400MHz DDR) at the lowest supported memory timings that our Mushkin PC3500 Level 2 memory will support:

Stable DDR400 Timings — 2 DIMMs (2/3 DIMMs populated)
Clock Speed:	200MHz
Timing Mode:	N/A
CAS Latency:	2.0
Bank Interleave:	N/A
RAS to CAS Delay:	2T
RAS Precharge:	6T
Precharge Delay:	2T
Command Rate:	N/A

We had no problem running 2 DS 512MB DIMMs of our standard Mushkin PC3500 Level2 in the SiS755 Reference Board. We were also able to run the memory test suite with complete stability at 2-2-2-6 timings. Tests with some demanding games other than our tests suite, however, required RAS-to-CAS to be slowed to 3 for most stable operation. We also tested the SiS755 with just one DIMM and found timing requirements for one or two DIMMs to be the same.

Filling all available memory banks is more strenuous on the memory subsystem than testing 2 DIMMs, and, unlike some experiences with other Athlon 64 chipsets, 3 DS DIMMs worked just fine on the SiS755. We did have to lower memory timings to 2-2-3-6 for stable operation with 3 DIMMs, but this is a very small decrease.

Stable DDR400 Timings — 3 DIMMs (3/3 DIMMs populated)
Clock Speed:	200MHz
Timing Mode:	N/A
CAS Latency:	2.0
Bank Interleave:	N/A
RAS to CAS Delay:	3T
RAS Precharge:	6T
Precharge Delay:	2T
Command Rate:	N/A

We tested the memory timings with both 2 and 3 banks filled using several stress tests and general applications to guarantee stability. Prime95 torture tests were successfully run at the timings listed in the above charts. We also ran ScienceMark (memory tests only) and Super Pi. None of the three stress tests created any stability problems for the SiS755 Reference Board at these memory timings.

While it was good to see the SiS able to run with 3 DS DIMMs installed, we did notice unusual latencies when testing with 3 DIMMs in ScienceMark 2.0. While performance was completely stable with 3 DIMMs, latency with 3 DIMMs is almost twice the latency with 2 DIMMs. Since the latency numbers with the SiS had been quite good in tests, we looked a little deeper into what was going on here. Interestingly, latencies tested virtually the same with either one or two DS DIMMs installed. However, once a 3rd DIMM was added, whether single- or double-sided, the latency and memory bandwidth dropped to about half the values with 1 or 2 DIMMs. This may be an issue with just the SiS755 Reference board, and we plan to look at this further on production boards. For now, up to 4 sides (2 DS DIMMs) could be used with top performance. Using 5 or 6 sides (3 DS DIMMs or 2 DS and a single-sided) increased latency significantly. Our advice, until we can test this further on production boards, is to limit memory to 4 sides for best performance with the SiS755.