Intel's Pentium 4 E: Prescott Arrives with Luggage
by Anand Lal Shimpi & Derek Wilson on February 1, 2004 3:06 PM EST- Posted in
- CPUs
An Impatient Prescott: Scheduler Improvements
Prescott can’t keep any more operations in flight (active in the pipeline) than Northwood, but because of the longer pipeline Prescott must work even harder to make sure that it is filled.
We just finished discussing branch predictors and their importance in determining how deep of a pipeline you can have, but another contributor to the equation is a CPU’s scheduling windows.
Let’s say you’ve got a program that is 3 operations long:
1. D = B + 1
2. A = 3 + D
3. C = A + B
You’ll notice that the 2nd operation can’t execute until the first one is complete, as it depends on the outcome (D) of the first operation. The same is true for the 3rd operation, it can’t execute until it knows what the value of A is. Now let’s say our CPU has 3 ALUs, and in theory could execute three adds simultaneously, if we just had this stream of operations going through the pipeline, we would only be using 1/3 of our total execution power - not the best situation. If we just upgraded from a CPU with 1 ALU, we would be getting the same throughput as our older CPU – and no one wants to hear that.
Luckily, no program is 3 operations long (even print “Hello World” is on the order of 100 operations) so our 3 ALUs should be able to stay busy, right? There is a unit in all modern day CPUs whose job it is to keep execution units, like ALUs, as busy as possible – as much of the time as possible. This is the job of the scheduler.
The scheduler looks at a number of operations being sent to the CPU’s execution cores and attempts to extract the maximum amount of parallelism possible from the operations. It does so by placing pending operations as soon as they make it to the scheduling stage(s) of the pipeline into a buffer or scheduling window. The size of the window determines the amount of parallelism that can be extracted, for example if our CPU’s scheduling window were only 3 operations large then using the above code example we would still only use 1/3 of our ALUs. If we could look at more operations, we could potentially find code that didn’t depend on the values of A, B or D and execute that in parallel while we’re waiting for other operations to complete. Make sense?
Because Intel increased the size of the pipeline on Prescott by such a large amount, the scheduling windows had to be increased a bit. Unfortunately, present microarchitecture design techniques do not allow for very large scheduling windows to be used on high clock speed CPUs – so the improvements here were minimal.
Intel increased the size of the scheduling windows used to buffer operations going to the FP units to coincide with the increase in pipeline.
There is also parallelism that can be extracted out of load and store operations (getting data out of and into memory). Let’s say that you have the following:
A = 1 + 3
Store A at memory location X
…
…
Load A from memory location X
The store operation actually happens as two operations (further pipelining by splitting up a store into two operations): a store address operation (where the data is going) and a store data operation (what the data actually is). The problem here is that the scheduler may try to parallelize the store operations and the load operation without realizing that the two are dependent on one another. Once this is discovered, the load will not execute and a performance penalty will be paid because the CPU’s scheduler just wasted time getting a load ready to execute and then having to get rid of it. The load will eventually execute after the store operations have completed, but at a significant performance penalty.
If a situation like the one mentioned above does crop up, long pipeline designs will suffer greatly – meaning that Prescott wants this to happen even less than Northwood. In Prescott, Intel included a small, very accurate, predictor to predict whether a load operation is likely to require data from a soon-to-be-executed store and hold that load until the store has executed. Although the predictor isn’t perfect, it will reduce bubbles of no-execution in the pipeline – a killer to Prescott and all long pipelined architectures.
Don’t look at these enhancements to improve performance, but to help balance the lengthened pipeline. A lot of the improvements we’ll talk about may sound wonderful but you must keep in mind that at this point, Prescott needs these technologies in order to equal the performance of Northwood so don’t get too excited. It’s an uphill battle that must be fought.
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TrogdorJW - Tuesday, February 3, 2004 - link
Technically, it depends on how you cound pipelines. The P4 has several "simple" pipelines that deal with the easy instructions, and then "complex" pipelines that deal with the more difficult instructions.For example, they have two Integer units running at twice the core clock speed, but those only do simple integer instructions. Then they have a complex Integer unit running at core speed that can do the remaining integer instructions. So that's 3 INT units, technically, and two of those are double-pumped, so you could even call it five INT units if you want to be generous.
The FP/SSE is somewhat similar, I believe. The end result is that it's not an apples-to-apples comparison between Intel and AMD pipelines. You could really say both of them have nine different execution units (pipelines), but Intel's pipelines aren't as powerful as AMD's when compared directly. See: http://www.tomshardware.com/cpu/20040201/prescott-... - there is an image of the pipelines in the Prescott, which is mostly unchanged from the Northwood.
The thing with the number of stages in a pipeline still holds true. So you have 60 million transistors in 7 pipelines, each with 31 stages. (Actually, the FP pipelines probably have more stages.) That still gives you a rough guess of 275000 transistors in each pipeline stage. In the P4, it was 30 million transistors in 20 stages and still 7 pipelines, giving a guess of 215000 transistors per stage.
I'm really, REALLY curious as to what Intel is doing. For some reason, the core of the P4 in the Prescott is at least twice as big (in transistor count) as the core of the Northwood. The L2 cache is also twice as big. So we went from 29+26 million transistors in Northwood (core+L2 cache) to apparently something like 75+50 in the Prescott.
If indeed there are 75 million transistors in the Prescott core, they *had* to increase the length of the pipelines to 30 or so stages to have any chance of running fast. However, you can't argue that the increase in transistors was necessitated by the increase in the number of pipeline stages! Why? Apparently, the Prescott has more transistors per stage, so in theory a Northwood would have actually scaled to *higher* clockspeeds than a Prescott!
Intel is definitely not showing all of their cards on the table right now. I'm betting that they're trying to protect Itanium as long as they can. I guess we'll know sometime in the next year or so.
KristopherKubicki - Tuesday, February 3, 2004 - link
Check out Anand's Blog on x86-64 for Intelhttp://www.anandtech.com/weblog/index.html?bid=46
Kristopher
Pumpkinierre - Tuesday, February 3, 2004 - link
Errata for #87 2nd paragraph: 'According to Ace's'- not Ace's but X-bit:http://www.xbitlabs.com/articles/cpu/display/presc...
Thank you #89 although I didnt think the P4 had as many pipelines as you quote.
INTC - Tuesday, February 3, 2004 - link
http://69.56.255.194/?article=13959Hmmm - wouldn't that be exciting? P4 Prescott 3.2E GHz with XDR Rambus at 3.2 GHz PCI Express and 64-bit extensions at IDF - I wonder when Nventiv will have that in their new Cold Fusion systems?
DerekBaker - Tuesday, February 3, 2004 - link
On the most common way of counting the Athlon has 9 pipelines, the P4 7.Derek
Pumpkinierre - Tuesday, February 3, 2004 - link
Add "So to compensate the slower speed of shorter pipelines, they make them more numerous in a cpu eg 6-8 in Athlons cf. 3 in P4 (I believe)" to the middle of 1st paragraphPumpkinierre - Tuesday, February 3, 2004 - link
#82 There is more than one pipeline in a processor so you have to take that into account in your stage/No. of transistor calculations plus registers, buffers, stacks, MMX, SSE etc.. I also am not totally happy with the AT explanation of pipelines. Pipelines are just a way of guessing the correct answer so that idle cpu time can be put to good use. I thought the stages in a pipeline be it 10 or 20 were of the same complexity. Its just that the outcome of a longer pipeline had a lower probability of being correct due to the increased likelihood of more branch statements being present in a longer pipeline. But work in checking the correct outcome is less in a longer pipeline. Work is heat so smaller pipelines make more heat which lessens speed headroom while longer pipelines can run at higher speed but correct outcomes are less probable. So to compensate they use more pipelines. Paradoxically with Prescott they've increased the pipeline lenght but they have more heat so as far as I am concerned speed headroom is limited and I doubt they will get past 4Gig with the present cpu. The o'clocks so far bear this out, with stable bests at ~3.8GHz. This is as result of some physical problem with the 90 nm process. What they should have done is applied the tweaks to the Northwood 130nm core and they would have been heaps better off. Its doubtful whether the tweaks would have increased temperature but they would be getting 30 to 50% better calculating power from the cpu at the same core speed. Would'nt need to PR rate it, just call it a different name. Then they would have had more time to sort out the 90nm problem while keeping the consumer happy. As it is they are going to cop a lot of flak over this overbaked failure.I'm also not happy about this loss of latency in the caches. Even though i've abused large caches in the past, that was on the grounds of gaming software where i expected alot of cache misses by the cpu because of the unpredictable nature of operator driven gaming. But here they are saying the latency has increased (and tests measure this) no matter the application and the reason given by sites is the doubling in size of the cache. But when the P4 went from 256K L2 to 512k L2 and the A-XP(256K) to Barton(512K) or even A64 3000+(512K) and 3200+(1024K) no major increase in cache latency was reported- in fact often the opposite. According to Ace's the latency of the Prescott 16K data L1 cache is now close to that of the a64 L1 (64K data) 4 times its size and double the latency of the Northwood 9even though Intel says it is the same- but no figures)! Something weird's going on with this 90nm stuff.
PrinceGaz - Tuesday, February 3, 2004 - link
Hmmm... where to begin :)Okay, first of all I must say that was an excellent review overall and the background material covering all the architectural changes was nothing short of superb. I'll definitely re-read chunks of that whenever I need a refresher on various aspects of its design.
Your overclocking results were very good, far better than those achieved by most other sites. However I think it was a bad idea for AnandTech to suggest a Prescott is a great overclocker based on the sample(s) they received from Intel. It would be better to wait until you've got some retail CPUs from other sources before making recommendations about buying it for overclocking as readers may not be so lucky as you were.
Right, onto the tests... overall as I see it the Prescott is really pretty much on a par with the Northwood performance-wise for a given clock-speed. Its faster at some tasks by a small margin thats not significant, and slower at as many others by a similar small margin I wouldn't worry about. As such it won't matter to an average user whether they get a P4 3.4C or a P4 3.4E processor. Therefore everything that has been said comparing the Northwood to the A64 is still valid when comparing the Prescott to the A64 (at least at clock-speeds over 3GHz).
As many others have commented, the omission of any mention at all of the thermal issues was nothing short of staggering. *Every* other major review I read at least said something about it and most of them had quite a lot to say about it. I did notice the occassional error in what they said such as at [H]ard where their Prescott was running at 1.5V which therefore invalidated their temperature readings but even on those sites where it was running at the correct voltage, heat was still an issue.
Its quite possible the current version of the Prescott is a bit like AMD's first 130nm chip the Thoroughbred 'A' which also ran rather hot. Of course this is already supposed to be the third revision of the Prescott so whether they can make any further tweaks that will seriously reduce power requirements is debatable. If they can't then ramping up the speed up to 4GHz and beyond that in 2005 will be a major problem. The most conservative estimate based on current figures would be for a 4GHz chip to have a TDP of 130W though in reality thats likely to be closer to 150W. Even if improved cooling solutions are able to get rid of that much heat from the chip *and* the case, electricity isn't free so the cost of running it must be considered to.
Finally about 64-bit support in the Prescott. It wouldn't surprise me if Prescott does have 64-bit support built into it which is currently disabled in much the same way Hyper-Threading was disabled in some Northwood cores. The only people who know for sure either work for Intel and arent saying, or are under NDA. It would be a blow to IA64 (and also in a way be seen as saying AMD was right) if Intel did suddenly enable x86-64 support so I doubt they'll do so unless the case becomes compelling. Theres no sign of that happening in the immediate future.
KristopherKubicki - Tuesday, February 3, 2004 - link
They put 30M extra transistors on there to confuse people. :(Kristopher
TrogdorJW - Tuesday, February 3, 2004 - link
Actually, Icewind, if they don't *have* to activate the 64-bit capability, then they're okay. I mean, activating 64-bit in x86 is basically the death toll for Itanium and IA-64. That would make some (*all*?) of the companies that have purchased and worked on IA-64 rather pissed, right?If Prescott does have 64-bit, it was just Intel hedging their bets. They would have started design on the new core 2 years ago, around the time when the full specifications of AMD64 were released. Intel couldn't know for sure what the final result of K8 would be, so they may have decided to start early, just in case.
Like I said before, it's pure speculation at this point, but I figure adding 64-bit registers and instructions to x86 could be done with 10 to 15 million transistors "easily". I've basically figured out (as others have, apparently) that there are close to 30 million transistors that aren't accounted for in the Prescott. That's the size of the entire Northwood core (minus cache)! If you have a better idea of where these transistors were used, feel free to share it. :)