Socket 939 Chipsets: Motherboard Performance & PCI/AGP Locks

How Does the VIA PCI/AGP Lock Work?

As we talked to more manufacturers at Computex, we became concerned about what might become a serious problem for many of our readers - a VIA AGP/PCI lock on the K8T800 PRO that either does not work at all or one that does not work as intended, providing only very limited overclocking abilities. Anand contacted VIA and talked with engineers to try to find out how the lock was constructed and to try to determine what might be wrong with the K8T800 PRO chipsets that were starting to find their way to manufacturers.

The K8T800 PRO is capable of operating in two modes: synchronous or asynchronous. In synchronous mode, all of the clocks in the system are derived from one external clock generator producing a 66MHz signal. The diagram below can help explain this:

The external clock generator actually produces two clock signals: a 200MHz and a 66MHz signal. The 200MHz signal is used for the initial handshake with the CPU, but the actual running HT frequency is derived from the 66MHz clock input to the North Bridge. The K8T800 PRO North Bridge has an internal clock generator that takes the 66MHz input clock and produces a 200MHz clock, which it then feeds to the Hyper Transport interface within the chip (which in turn sets the CPU clock frequency).

The AGP frequency in this case is also derived from the 66MHz input clock, as is the PCI frequency. When you increase the HT frequency of your K8T800 PRO motherboard operating in synchronous mode, the 66MHz clock is actually what's being adjusted, and thus, all of the clocks including the AGP and PCI clocks are adjusted as well. Obviously for overclocking, this isn't desirable, since the max attainable overclock is now limited by how high your AGP and PCI devices can be overclocked. To put it in perspective, in synchronous mode, most systems will be limited to a 219MHz Hyper Transport overclock, while a working asynchronous mode (AGP/PCI lock) can allow overclocks of close to 280MHz (see nForce3 250 overclocking tests).

One feature of the K8T800 PRO is its support for asynchronous operation through the use of an AGP/PCI lock. The diagram below describes what happens in asynchronous mode:

Here, you see that a second 200MHz clock is generated externally and also fed into the North Bridge. This 200MHz clock is used solely for the Hyper Transport interface, while the 66MHz clock remains present to drive the AGP and PCI interfaces. Thus, when you increase your HT frequency in asynchronous mode, only the 200MHz clock is touched, while the 66MHz clock remains constant.

So, why is it that VIA's AGP/PCI lock doesn't work all the time? Architecturally, from a high level, everything seems fine. But as simple as our explanation here may be, actually implementing a multi-clock environment is quite difficult. Designs like this require very complicated clock trees that ensure all parts of the chipset receive the same clock signal at the same time. Introducing a second clock to some of the components complicates things even more, as you now have multiple clock trees to deal with and the components running off of different clocks still need to communicate with one another as fast as possible.

Without having low level access to the chipset, your guess is as good as ours as to what's wrong with VIA's AGP/PCI lock. VIA just recently started working on the problem and is searching for a solution, but without even knowing the solution themselves, it's hard to tell whether it can be fixed via a BIOS update or if it will require another revision of the chipset.