Intel Celeron D: New, Improved & Exceeds Expectations

Under The Hood of Celeron D

For an in-depth look at what's different with the new Celeron, the first 11 or so pages of our Pentium 4 E (Prescott) launch article do an excellent job of covering the bases. For a quick summary, here's a look at the major changes inside the Prescott core:

• 90nm Strained Silicon Process - more, faster transistors in less space
• 31 Pipeline Stages - for clock speed ramping
• Improved Branch Predictor - helps avoid pipeline stall
• Improved Scheduler - helps avoid doing unnecessary work
• Improved Execution Core - added integer multiply and fast shift to ALU
• Larger, Slower Caches - higher latency caches for speed and size scaling
• SSE3 - 13 new instructions

The Celeron D gets an additional bonus of an FSB speed increase from 400MHz to 533MHz as well.

Even with the ominous 31-stage pipeline and higher latency caches, we get better performance with the new Celeron D. So, how does all this stack up to make Prescott a better Celeron than Northwood? Well, let's take it step by step.

First of all, the 16kb L1 cache size of Prescott has a significant impact on the Celeron. Northwood based Celerons only have 8kb of L1 cache. With 8kb more of the on die data stored "closer" (in terms of latency) to the processor, we will definitely see more cache hits get to the processor quicker in spite of the fact that cache latency on Celeron D is the same as Pentium 4 E. Prescott's cache latency is much higher than Northwood's. Improving this ability to recover is critical, as eventhough Celeron D has an increased L2 cache, the size of on die memory is still small and cache misses will occur more than on the Pentium 4.

When dealing with a processor short on cache and prone to very painful pipeline stalls, improving the average cache hit latency can really help to keep extra stalls from happening (a fast L2 hit will come back in about 25 cycles on Prescott), and can help to refill the pipeline once its stalled (as more data will be able to get back into the pipeline faster).

This 8kb of extra L1 cache is a much smaller portion of Pentium 4's total cache size. Since Pentium 4 E has fewer cache misses than Celeron D (it has 4 times the L2 cache), improvements to the L1 cache size don't have as much opportunity to shine.

Speaking of L2, the Celeon D has received an increase from 128kb in the current Celeron to 256kb. Even though this is still a quarter of the (still insufficient) 1MB cache the Pentium 4 E has, we aren't going to see the same type of performance drop we saw when moving from the Northwood Pentium 4 to Celeron (which also had a quarter of its big brother's cache). The reason is the number of cache hits we will see increase rapidly and hit a point of diminishing returns after a certain size. The curve is similar to a logarithmic curve (benefits increase rapidly as cache size increases at first, but then level off quickly).

What it comes down to is that doubling a small cache (say, going from 128kb to 256kb) will have a much higher impact on performance (because the number of cache hits is significantly increased) than doubling a larger cache (like going from 512kb to 1MB). In other words, P4 E gets less benefit from its doubled L2 cache than Celeron D.

While we're on the subject of caches and memory, the 533MHz frontside bus effectively gets data from memory to the processor faster in case of a cache miss. This is very important in the low- cache environment of the Celeron world. Unfortunately, we couldn't increase our multiplier and run our 2.8 GHz Celeron 335 at 28x100 to see just what kind of impact bus speed has on the new processor.

The enhancements Intel made to branch prediction and scheduling round out the factors that help make Prescott an excellent Celeron core. Since we're working with a small L2 cache, it is excessively important to work with good data and avoid stalls for reasons other than cache misses. Northwood is at a disadvantage to Prescott here. Better branch prediction will help avoid filling the cache with data from a mis-predicted branch as well as aid in averting unnecessary bubbles in the pipeline for the same reason. Better scheduling means more efficient use of the data available to the processor as well. Northwood is stuck on these two counts. Adding an integer multiply and fast shift/rotate to Prescott also helped the Celeron D maintain a high level of efficiency, but this really shouldn't have any greater impact on Celeron D than on Pentium 4.

It all comes down to being resilient and efficient. Northwood is very dependent on its L2 cache size. The enhancements Intel made to Prescott in order to avoid that large negative impact of adding so many pipeline stages really benefit the processor when it is starved for data. Prescott has to be more careful not to stall just to keep up with the current Pentium 4 line. As a result, the Celeron flavor can deal with tighter constraints on L2 cache size, which help even more when paired with a larger cache than the Northwood derived version.