<b>Updated</b> CPU Cheatsheet - Seven Years of Covert CPU Operations
by Jarred Walton on August 28, 2004 9:00 AM EST- Posted in
- CPUs
AMD Cheat Sheet
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| AMD Processors | ||||||||||
| Argon (K7) | Athlon | Slot A | 500-700 | 512K | 22 + cache | 250 | 184 | 100 | ||
| Pluto (K75) | Athlon | Slot A | 550-850 | 512K | 22 + cache | 180 | 102 | 100 | ||
| Orion (K75) | Athlon | Slot A | 900-1000 | 512K | 22 + cache | 180 | 102 | 100 | ||
| Spitfire | Duron | 462 | 600-950 | 64K | 25 | 180 | 100 | 100 | ||
| Morgan | Duron | 462 | 900-1300 | 64K | 25.2 | 180 | 106 | 100 | ||
| Thunderbird | Athlon "B" | 462 | 650-1400 | 256K | 37 | 180 | 117 | 100 | ||
| Thunderbird | Athlon "C" | 462 | 1000-1400 | 256K | 37 | 180 | 117 | 133 | ||
| Palomino | Athlon XP/M | 462 | 850-1733 | 256K | 37.5 | 180 | 129 | 100/133 | ||
| Palomino | Athlon MP | 462 | 1000-1733 | 256K | 37.5 | 180 | 129 | 100/133 | 1-2 | |
| Thoroughbred A | Athlon XP | 462 | 1467-1833? | 256K | 37.5 | 130 | 80 | 133 | ||
| Thoroughbred B | Athlon XP/M | 462 | 1200-2133 | 256K | 37.5 | 130 | 84 | 133 | ||
| Thoroughbred B | Athlon XP | 462 | 2083-2250 | 256K | 37.5 | 130 | 84 | 166 | ||
| Thoroughbred B | Athlon MP | 462 | 1667-2133 | 256K | 37.5 | 130 | 84 | 133 | 1-2 | |
| Barton | Athlon XP/M | 462 | 1467-2133 | 512K | 54.3 | 130 | 101 | 133 | ||
| Barton | Athlon XP | 462 | 1833-2167 | 512K | 54.3 | 130 | 101 | 166 | ||
| Barton | Athlon XP | 462 | 2100-2200 | 512K | 54.3 | 130 | 101 | 200 | ||
| Barton | Athlon MP | 462 | 2133 | 512K | 54.3 | 130 | 101 | 166 | 1-2 | |
| Applebred | Duron | 462 | 1400-1800 | 64K | 25.2* | 130 | 84* | 133 | ||
| Thorton | Athlon XP | 462 | 1667-2067 | 256K | 37.5* | 130 | 101* | 133 | ||
| Thoroughbred B | Sempron | 462 | 1500-2000+ | 256K | 37.5 | 130 | 84 | 166 | ||
| Sledgehammer | Athlon FX | 940 | 2200-??? | 1024K | 105.9 | 130 SOI | 193 | 200 | Y | |
| Sledgehammer | Opteron | 940 | 1400-2400 | 1024K | 105.9 | 130 SOI | 193 | 200 | Y | 1-8 |
| Sledgehammer | Athlon FX | 939 | 2400-??? | 1024K | 105.9 | 130 SOI | 193 | 200 | Y | |
| Clawhammer | Athlon 64 | 754 | 1800-2200(?) | 512K | 105.9 | 130 SOI | 193 | 200 | Y | |
| Clawhammer | Athlon 64 | 754 | 2000-2400(?) | 1024K | 105.9 | 130 SOI | 193 | 200 | Y | |
| Newcastle | Athlon 64 | 754 | 1800-2600(?) | 512K | 68.5 | 130 SOI | 144 | 200 | Y | |
| Newcastle | Athlon 64 | 939 | 2200-2600(?) | 512K | 68.5 | 130 SOI | 144 | 200 | Y | |
| San Diego | Athlon FX | 939 | 2600-??? | 1024K | 105.9(?) | 90 SOI | 114(?) | 200 | Y | |
| Paris | Sempron | 754 | 1800-??? | 256K | ~50(?) | 130 SOI | 118 | 200 | N | |
| Venus | Opteron 1xx | 940 | 90 SOI | 200? | Y | |||||
| Troy | Opteron 2xx | 940 | 90 SOI | 200? | Y | 1-2 | ||||
| Athens | Opteron 8xx | 940 | 90 SOI | 200? | Y | 1-8 | ||||
| Odessa | Athlon 64 M? | 754? | 512K | 130 SOI | 200? | Y | ||||
| Winchester | Athlon 64 | 939 | 512K | 68.5(?) | 90 SOI | 83(?) | 200 | Y | ||
| Dublin | Athlon XP-M | 462 | 37.5 | 130 SOI | 128 | 200? | N | |||
| Newark | Athlon 64-M LP | 754? | 90 SOI | 200? | Y | |||||
| Lancaster | Athlon 64 M | 754? | 90 SOI | 200? | Y | |||||
| Georgetown | Athlon XP M | 462/754? | 90 SOI | 200? | N? | |||||
| Sonora | Athlon XP-M LP | 462/754? | 90 SOI | 200? | N? | |||||
| Denmark | Opteron 1xx | 940 | 90 SOI | 200? | Y | |||||
| Italy | Opteron 2xx | 940 | 90 SOI | 200? | Y | 1-2 | ||||
| Egypt | Opteron 8xx | 940 | 90 SOI | 200? | Y | 1-8 | ||||
| Toledo | Dual Core FX | 939 | 90 SOI | 200? | Y | 2C | ||||
| Palermo | Sempron (?) | 939 (?) | 256K? | ~50(?) | 90 SOI | 62(?) | 200 | N? | ||
| Oakville | Athlon 64 Mobile | 754? | 512K? | 90 SOI | 200? | Y | ||||
| Victoria | Sempron (?) | 754 (?) | 256K? | ~50(?) | 90 SOI | 62(?) | 200 | N? | ||
| * Die Size and/or transistor count is based off a larger CPU core with a portion of the die disabled. | ||||||||||
| ** Various steppings/sources listed different die sizes. | ||||||||||
| *** The bus speed all Athons/Durons is double-pumped, but the CPU multiplier is based off the listed speed. | ||||||||||
A few notes to clarify the information. The stated die sizes and transistor counts for the Applebred and Thorton reflect the fact that these processors are Thoroughbred and Barton cores, respectively, with half of the L2 cache disabled, which is why they have a single asterisk next to them. There have been reports of hacking the Thorton processors and turning them into full Barton CPUs, but considering the insignificant cost difference these days, it's probably not worth worrying about. AMD plans on discontinuing the Barton soon anyway, and will use the old Thoroughbred core for the Socket A Sempron chips.
Transistor counts on Paris, Victoria, and Palermo are likely off, but it remains to be seen how AMD actually configures these chips. Early Athlon 64 512K cache chips for socket 754 were Clawhammer cores with half the cache disabled, but the newer models (i.e. 3200+ at 2.2 GHz with 512K, 3400+ 2.4 GHz 512K, and 3700+ 2.6 GHz with 512K) appear to be actual Newcastle cores. The same could very well happen with the Paris cores, where initial shipments are "downgraded" Newcastle cores, and later versions may physically remove the ~18.7 million transistors used in the L2 cache. Regardless, values on these cores should be taken with a grain of salt.
Unreleased processors will likely change from these current estimates, and question marks indicate best guess data at present. If you notice any errors or if you have additional information on forthcoming processors, let us know in the comments section or email.
Take note of the Toledo, Denmark, Italy, and Egypt cores; the 2C next to it stands for dual core. All four models use the same basic core and should come out around the same time in early 2005. Whether they launch as planned remains to be seen, and precise details about the internal layout are not yet clear - recent news suggests that each core will have its own L2 cache. Dual core is best described as SMP on a single chip, and while on the subject of SMP, please note that all of the Athlon XP processors could support multi-processor configurations unofficially. 2-way SMP was almost a certainty, but none of the CPUs were verified to function in such a configuration by AMD. While it would not be prudent to take such a risk as a business, quite a few enthusiasts saved themselves a lot of money by putting XP chips into SMP motherboards instead of spending the extra money on MP chips.
The basic core of the Athlon, from the Pluto all the way through the latest Newcastle and Paris processors, changed very little since its inception. It has a 10 stage integer pipeline and 15 stage floating point pipeline, with three identical Arithmetic/Logic Units (ALUs), Address Generation Units (AGUs), and Floating Point Units (FPUs). The FPUs also handle the MMX, 3DNow!/+, and SSE/SSE2 support. Opteron increased the length to 12/17 stages, in addition to bringing 64-bit support. Future versions of the Athlon 64 will likely increase the length of the pipeline past the current 12/17 stages in order to increase clock speeds, but I doubt that AMD will ever show the hubris of Intel by creating a 31 stage pipeline - at least, not on any iteration of the Athlon architecture. This is especially a problem with the increasing power leakage of high clockspeeds and increasingly small process technology. Until those issues are resolved, I think it's safe to say that pipeline lengths will stay in the 10 to 15 stages (for integers) range with AMD.
Update: One reader was good enough to send a link to AMD's site where they actually list the Opteron as being a 12/17 design. (Thanks Tom!) Finding any good details on the Intel and AMD sites can be a major chore, most likely due to the level of competition between the companies as well as their size. There's a rule somewhere that the larger a company gets, the less informative and helpful their web site becomes! For those that want the link, here's the Opteron information. That means that all Athlon 64 designs are also 12/17, of course. The Denmark, Italy, and Egypt CPUs are also dual core, it appears, and their entries have been updated to reflect this. (The old roadmap didn't include that information.)
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Maverick Shiva - Thursday, November 25, 2004 - link
The Articles are really beautiful.This was the complete description of the processors that are released and yet to be released.
The technical details are really awsome and minute to the Detail.
I would recommend that if you had Anand Tech.com then you are really tech Savvy.
JarredWalton - Saturday, September 18, 2004 - link
#72 - the article is now slightly outdated, being a whopping 20 days old. Sorry. We'll look at updating this with future articles, of course.Assimilator1 - Friday, September 17, 2004 - link
An excellent article:)Though as someone mentioned the Semperon 2300 is missing ,this is clocked at 1.583GHz.
Its listed in AMDs model 8 data sheets
endrebjorsvik - Wednesday, September 15, 2004 - link
A very nice article with lost of good information!!Is there anybody who has all these datas collected into somethong like an exel-file or something.
jenand - Wednesday, September 8, 2004 - link
JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:http://www.intel.com/design/itanium2/download/Madi...
jenand - Wednesday, September 8, 2004 - link
JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:http://www.intel.com/design/itanium2/download/Madi...
romanl - Tuesday, September 7, 2004 - link
Why is the Sempron 2300+ missing from a list of AMD CPUs?IntelUser2000 - Thursday, September 2, 2004 - link
It was said that Willamette has 33% superior branch prediction due to its 4KB BTB buffer compared to Pentium III's(P3's had 512B).It was also said Pentium M's have 20% superior branch prediction to previous generation. Since we know that the major enhancements on branch prediction for Pentium M is enhanced indirect branch prediction and no BTB buffer increase, its likely its 20% over P3.
Dothan does have superior branch prediction to 0.13 micron Pentium M, but it would probably be minor compared to Pentium 4's 33% superiority over P3.
Taking P3 as baseline,
-Pentium 4 adds 33% using 8x increase in BTB buffer, or 4KB compared to 512B
-Banias takes P3 and puts enhancements to indirect branch predictor, which gives 20%
-Prescott takes 33% from Willamette AND 20% from Banias
-Dothan has Banias' 20% improvements plus something minor
You say: " However, with the doubling of the cache size on Dothan, I can't imagine Intel would leave it with inferior branch prediction."
Yeah but I can't imagine that Prescott will have inferior branch prediction than Dothan since its needed more on Prescott. And looking at per clock enhancements Dothan is not much faster than Banias, except Content Creation apps, telling again the enhancements are minor.
Remember we are talking about how superior one branch predictor would be over another with same pipelines.
I think of it this way: In terms of worst to best
Pentium III
Banias
P4 Willamette/Northwood/Dothan(I still think 33% improvement over P6 is greater than 20% in Banias+Dothan improvements)
Prescott
Oh yeah, there will be 4MB Fanwood parts but at 1.6GHz.
Also since Itanium's core is half the size of Xeon and Intel also mentioned there will be twice the number of cores that Xeon has and Tukwila will be introduced ~2007 with quad-core Xeon then, Tukwila will have 8-core with Hyperthreading. Montecito is rumored to already have 600mm2 die size. Montecito has 24MB but Tukwila is rumored to have 32MB, not a lot increase, to possibly save space for more cores?
I mean, Sun plans 32-core designs.
Link: www.mikeshardware.co.uk
JarredWalton - Wednesday, September 1, 2004 - link
Jenand, just an update, but it appears that Fanwood might not have 9M parts. The latest Intel roadmap talks about "Madison 9M/Fanwood/LV" parts in several places, but all the actual Fanwood parts are listed as 3M parts, and there's a not about pushing back the Fanwood 4M part.What is Fanwood? As of right now, I'm really not sure. Initially, I thought it was a renamed Madison, perhaps with more cache or for LV environments. Now, I'm starting to wonder if it might be a 90 nm version of Madison, or a version with more metal layers. Clock speeds are still in the Madison range, so that wouldn't really make sense, but why have the separate name if it's not somehow fundamentally different from Madison?
And for what it's worth, the charts are now outdated somewhat with the announcement of the 6xx series of 2M L2 Pentium 4 parts. See latest Insider Stories.
jenand - Wednesday, September 1, 2004 - link
Yes, Fanwood looks to be a 9MB L3 part. Strange. But i is limited to DP servers while Madison9M is for MP servers. just like Xeon MP end DP I guess.And no not many care about IA64 these days. Not strange. But with Millington I assume that will change! ;)