AMD Cheat Sheet

AMD Processors
Argon (K7)AthlonSlot A500-700512K22 + cache250184100 
Pluto (K75)AthlonSlot A550-850512K22 + cache180102100 
Orion (K75)AthlonSlot A900-1000512K22 + cache180102100 
SpitfireDuron462600-95064K25180100100 
MorganDuron462900-130064K25.2180106100 
ThunderbirdAthlon "B"462650-1400256K37180117100 
ThunderbirdAthlon "C"4621000-1400256K37180117133 
PalominoAthlon XP/M462850-1733256K37.5180129100/133 
PalominoAthlon MP4621000-1733256K37.5180129100/1331-2
Thoroughbred AAthlon XP4621467-1833?256K37.513080133 
Thoroughbred BAthlon XP/M4621200-2133256K37.513084133 
Thoroughbred BAthlon XP4622083-2250256K37.513084166 
Thoroughbred BAthlon MP4621667-2133256K37.5130841331-2
BartonAthlon XP/M4621467-2133512K54.3130101133 
BartonAthlon XP4621833-2167512K54.3130101166 
BartonAthlon XP4622100-2200512K54.3130101200 
BartonAthlon MP4622133512K54.31301011661-2
ApplebredDuron4621400-180064K25.2*13084*133 
ThortonAthlon XP4621667-2067256K37.5*130101*133 
Thoroughbred BSempron4621500-2000+256K37.513084166 
SledgehammerAthlon FX9402200-???1024K105.9130 SOI193200Y 
SledgehammerOpteron9401400-24001024K105.9130 SOI193200Y1-8
SledgehammerAthlon FX9392400-???1024K105.9130 SOI193200Y 
ClawhammerAthlon 647541800-2200(?)512K105.9130 SOI193200Y 
ClawhammerAthlon 647542000-2400(?)1024K105.9130 SOI193200Y 
NewcastleAthlon 647541800-2600(?)512K68.5130 SOI144200Y 
NewcastleAthlon 649392200-2600(?)512K68.5130 SOI144200Y 
San DiegoAthlon FX9392600-???1024K105.9(?)90 SOI114(?)200Y 
ParisSempron7541800-???256K~50(?)130 SOI118200N 
VenusOpteron 1xx94090 SOI200?Y 
TroyOpteron 2xx94090 SOI200?Y1-2
AthensOpteron 8xx94090 SOI200?Y1-8
OdessaAthlon 64 M?754?512K130 SOI200?Y 
WinchesterAthlon 64939512K68.5(?)90 SOI83(?)200Y 
DublinAthlon XP-M46237.5130 SOI128200?N 
NewarkAthlon 64-M LP754?90 SOI200?Y 
LancasterAthlon 64 M754?90 SOI200?Y 
GeorgetownAthlon XP M462/754?90 SOI200?N? 
SonoraAthlon XP-M LP462/754?90 SOI200?N? 
DenmarkOpteron 1xx94090 SOI200?Y 
ItalyOpteron 2xx94090 SOI200?Y1-2
EgyptOpteron 8xx94090 SOI200?Y1-8
ToledoDual Core FX93990 SOI200?Y2C
PalermoSempron (?)939 (?)256K?~50(?)90 SOI62(?)200N? 
OakvilleAthlon 64 Mobile754?512K?90 SOI200?Y 
VictoriaSempron (?)754 (?) 256K?~50(?)90 SOI62(?)200N? 
* Die Size and/or transistor count is based off a larger CPU core with a portion of the die disabled.
** Various steppings/sources listed different die sizes.
*** The bus speed all Athons/Durons is double-pumped, but the CPU multiplier is based off the listed speed.

A few notes to clarify the information. The stated die sizes and transistor counts for the Applebred and Thorton reflect the fact that these processors are Thoroughbred and Barton cores, respectively, with half of the L2 cache disabled, which is why they have a single asterisk next to them. There have been reports of hacking the Thorton processors and turning them into full Barton CPUs, but considering the insignificant cost difference these days, it's probably not worth worrying about. AMD plans on discontinuing the Barton soon anyway, and will use the old Thoroughbred core for the Socket A Sempron chips.

Transistor counts on Paris, Victoria, and Palermo are likely off, but it remains to be seen how AMD actually configures these chips. Early Athlon 64 512K cache chips for socket 754 were Clawhammer cores with half the cache disabled, but the newer models (i.e. 3200+ at 2.2 GHz with 512K, 3400+ 2.4 GHz 512K, and 3700+ 2.6 GHz with 512K) appear to be actual Newcastle cores. The same could very well happen with the Paris cores, where initial shipments are "downgraded" Newcastle cores, and later versions may physically remove the ~18.7 million transistors used in the L2 cache. Regardless, values on these cores should be taken with a grain of salt.

Unreleased processors will likely change from these current estimates, and question marks indicate best guess data at present. If you notice any errors or if you have additional information on forthcoming processors, let us know in the comments section or email.

Take note of the Toledo, Denmark, Italy, and Egypt cores; the 2C next to it stands for dual core. All four models use the same basic core and should come out around the same time in early 2005. Whether they launch as planned remains to be seen, and precise details about the internal layout are not yet clear - recent news suggests that each core will have its own L2 cache. Dual core is best described as SMP on a single chip, and while on the subject of SMP, please note that all of the Athlon XP processors could support multi-processor configurations unofficially. 2-way SMP was almost a certainty, but none of the CPUs were verified to function in such a configuration by AMD. While it would not be prudent to take such a risk as a business, quite a few enthusiasts saved themselves a lot of money by putting XP chips into SMP motherboards instead of spending the extra money on MP chips.

The basic core of the Athlon, from the Pluto all the way through the latest Newcastle and Paris processors, changed very little since its inception. It has a 10 stage integer pipeline and 15 stage floating point pipeline, with three identical Arithmetic/Logic Units (ALUs), Address Generation Units (AGUs), and Floating Point Units (FPUs). The FPUs also handle the MMX, 3DNow!/+, and SSE/SSE2 support. Opteron increased the length to 12/17 stages, in addition to bringing 64-bit support. Future versions of the Athlon 64 will likely increase the length of the pipeline past the current 12/17 stages in order to increase clock speeds, but I doubt that AMD will ever show the hubris of Intel by creating a 31 stage pipeline - at least, not on any iteration of the Athlon architecture. This is especially a problem with the increasing power leakage of high clockspeeds and increasingly small process technology. Until those issues are resolved, I think it's safe to say that pipeline lengths will stay in the 10 to 15 stages (for integers) range with AMD.

Update: One reader was good enough to send a link to AMD's site where they actually list the Opteron as being a 12/17 design. (Thanks Tom!) Finding any good details on the Intel and AMD sites can be a major chore, most likely due to the level of competition between the companies as well as their size. There's a rule somewhere that the larger a company gets, the less informative and helpful their web site becomes! For those that want the link, here's the Opteron information. That means that all Athlon 64 designs are also 12/17, of course. The Denmark, Italy, and Egypt CPUs are also dual core, it appears, and their entries have been updated to reflect this. (The old roadmap didn't include that information.)

Index Intel Processors
Comments Locked

74 Comments

View All Comments

  • JarredWalton - Friday, August 27, 2004 - link

    Regarding pipeline lengths on Intel products, there are numerous sources that state the P6 core was a 12 stage design. Perhaps the Interger pipeline was shorter and the FP was longer? I don't know for sure, but the majority of information I have read says P6 (PPro, P2, P3, Cel, Cel-2) were all the same core and were all 12 stages. Here's a link to one of the more authoritative CPU information guys that I have read, Jon "Hannibal" Stokes:

    http://arstechnica.com/cpu/004/pentium-1/pentium-1...
    http://arstechnica.com/cpu/004/pentium-2/pentium-2...

    Those contain a histort of the Pentium architecture. Unless you can provide a more definitive source for pipeline lengths, I tend to believe Hannibal. I also heard at the time the original P4 launched that it had "as few as 20 and as many as 28 stages, depending on the instruction being executed and other factors." Something like that. Most people stuck with the "20 stage" figure, but it has become increasingly clear that it was not a straight 20-stage design.
  • IntelUser2000 - Friday, August 27, 2004 - link

    Another correction: the article states 12-stage pipeline for P6 cores? No, its 10, I don't know why some people say P6 cores and its related processors have 12 stage pipelines(exception being PM, because they ARE a different architecture, just not radical as P4), when its 10!!!
  • IntelUser2000 - Friday, August 27, 2004 - link

    First, some corrections.

    mostlyprudent, P4 Willamette is only available up to 2000. They are actually available from 1300-2000. Over 2000 is Northwood cores, which have 512KB L2 cache and is 0.13 micron process.

    Second, why don't anybody seem to notice the pipeline numbers for Prescott on Page 6?

    "The Prescott further extended the NetBurst pipeline to 23 stages in addition to the 8 fetch/decode stages. For whatever reason, Intel generally describes the pipeline of the Prescott as 31 stages while only calling the earlier design a 20 stage pipeline."

    What the hell? Is it actually true? Can the writer, Jarred Walton, please answer this question? Did you just get the facts wrong or is it true that Prescott does have 23 stage pipelines?
  • FlameDeer - Tuesday, August 24, 2004 - link

    Thanks Jarred, very good article! Very useful and helpful processor performance comparison, much better than Intel "BMW" naming! :)

    Some small correction at page 3 Intel Cheat Sheet table:
    Entry no.3 Mendocino is 250nm, 154mm2 only
    Entry no.7 Deschutes Bus Speed is 66 MHz
  • JarredWalton - Tuesday, August 24, 2004 - link

    #36 - I suppose I should have been consistent with the bus speeds. Intel's really is quad-pumped and AMD's really is double pumped. Somehow along the way I redid the Intel side to have the quad pumped bus speed and I didn't redo the AMD side. The Netburst architecture likely benefits a little more from the increased bus speed, but if AMD certainly benefits as well. I'll include that in my updated version later this week. (My left wrist needs a rest. I don't want to risk carpal tunnel syndrome.)

    On the HyperTransport side of things, I really don't regard the HT bus speed as being that important. The old style bus (Athlon Socket A) was a 64-bit 400 MHz bus (200 MHz double-pumped - at least on the 3200+) while HyperTransport is a 16-bit 800 MHz bus. I think that's right, anyway. So 16-bit * 800 MHz (bidirectional) is the same as 400 MHz * 400 MHz (unidirectional). Bleh. Whatever the case, I'm pretty sure the HT bus doesn't really make for the A64 being faster. It helps out tremendously in the Opteron with multiple processors, but that's different.
  • johnsonx - Tuesday, August 24, 2004 - link

    to #38

    There are two Thoroughbred B AXP 2600's. 133/266FSB @ 2133 Mhz (multiplier 15), and 166/333FSB at 2083Mhz (multiplier 12.5). Yours sounds like a 166/333FSB model.

  • mrmorris - Tuesday, August 24, 2004 - link

    #15
    My 2600+ AMD XP runs 2083MHz and its Thoroughbred-B!
  • magratton - Monday, August 23, 2004 - link

    #34 - Sweet. The article made me remember all those years, and that post gave me a great chuckle. Peace! Being an avid comments reader (though not so much a contributor) it is good to finally put a name to a.. well.. a name. Peace!
  • mlittl3 - Monday, August 23, 2004 - link

    Jarred

    Don't mean to be persistent but I was wondering what your thoughts about the bus speed listings were.

    Should AMD Athlon processors be listed with bus speeds like 100, 133, 166, 200 MHz or should it be 200, 266, 333, 400 MHz? Likewise for the AMD Athlon 64, FX, Opteron. They use hypertransport running anywhere from 600 to 1000 MHz and don't advertise a bus speed since the memory controller is integrated (even though everyone knows its 200 MHz X multiplier).

    If the current listed speeds are the way it should be written, what about the Intel bus speeds of 400, 533, 800 and 1066 MHz? These really are 100, 133, 200 and 266 MHz when calculating the actual processor speed.

    Do the Intel quad speed bus speeds really reflect the actual bus speed wherease the AMD double bus speed do not?

    Just wanted to be clear. Thanks. Can't wait for the GPU cheat sheet.

    Mark
  • JarredWalton - Monday, August 23, 2004 - link

    Umm... crap, sort of let the cat out of the bag there. If the "JW" at the end of the other name didn't clue you in, it should be blatantly obvious who I am now. (Although only people that read the news and article comments are likely to have seen the name.)

Log in

Don't have an account? Sign up now