<b>Updated</b> CPU Cheatsheet - Seven Years of Covert CPU Operations

Intel Cheat Sheet

Intel IA32/EM64T Processors
Covington	Cel	Slot 1	266/300	8K+8K			7.5	350	118	66
Mendocino	Cel ("A")	Slot 1	266-433	16K+16K	128K		19	250	154	66	1-2
Mendocino	Cel ("A")	370	233-533	16K+16K	128K		19	250	154	66	1-2
Coppermine-128	Cel ("A")	370	533-766	16K+16K	128K		28*	180	106	66
Coppermine-128	Cel ("A")	370	800-1100	16K+16K	128K		28*	180	106	100
Klamath	P II	Slot 1	233-333	16K+16K	512K		7.5+37.2	350	203+L2	66	1-2
Deschutes	P II	Slot 1	266-333	16K+16K	512K		7.5+37.2	250	118+L2	66	1-2
Deschutes	P II	Slot 1	350-450	16K+16K	512K		7.5+37.2	250	118+L2	100	1-2
Deschutes	P II Xeon	Slot 2	400-450	16K+16K	512K		7.5+37.2	250	118+L2	100	1-2
Deschutes	P II Xeon	Slot 2	400-450	16K+16K	1M		7.5+74.4	250	118+L2	100	1-2
Deschutes	P II Xeon	Slot 2	450	16K+16K	2M		7.5+148.8	250	118+L2	100	1-2
Katmai	P III	Slot 1	450-600	16K+16K	512K		9.5+37.2	250	131+L2	100	1-2
Katmai	P III B	Slot 1	533-600	16K+16K	512K		9.5+37.2	250	131+L2	133	1-2
Tanner	P III Xeon	Slot 2	500, 550	16K+16K	512K		9.5+37.2	250	128+L2	100	1-8
Tanner	P III Xeon	Slot 2	500, 550	16K+16K	1M		9.5+74.4	250	128+L2	100	1-8
Tanner	P III Xeon	Slot 2	500, 550	16K+16K	2M		9.5+148.8	250	128+L2	100	1-8
Cascades**	P III Xeon	Slot 2	600-1000	16K+16K	256K		28.1	180	106-90	133	1-2
Cascades	P III Xeon	Slot 2	700	16K+16K	1M			180	210?	100	1-4
Cascades	P III Xeon	Slot 2	700, 900	16K+16K	2M			180	385	100	1-4
Coppermine**	P III	Slot 1	550-1000	16K+16K	256K		28.1	180	106-90	100	1-2
Coppermine**	P III B	Slot 1	533-1000	16K+16K	256K		28.1	180	106-90	133	1-2
Coppermine**	P III E	370	500-1100	16K+16K	256K		28.1	180	106-90	100	1-2
Coppermine**	P III EB	370	533-1133	16K+16K	256K		28.1	180	106-90	133	1-2
Tualatin	Cel ("A")	370	1000-1400	16K+16K	256K		28.1	130	80	100
Tualatin	P III	370	1000-1333	16K+16K	256K		28.1	130	80	133	1-2
Tualatin	P III S	370	1133-1400	16K+16K	512K		45.9	130	110?	133	1-2
Willamette	Cel-128	478	1700-1800	12Ku+8K	128K		36.5	180	217*	100
Willamette	P 4	423	1300-2000	12Ku+8K	256K		42	180	217	100
Willamette	P 4	478	1500-2400	12Ku+8K	256K		42	180	217	100
Foster	Xeon DP	603	1400-2000	12Ku+8K	256K		42	180	217	100	1-2
Foster	Xeon MP	603	1400, 1500	12Ku+8K	256K	512K	42+37?	180		100	1-4
Foster	Xeon MP	603	1600	12Ku+8K	256K	1M	42+74?	180		100	1-4
Northwood	Cel	478	1400-2800	12Ku+8K	128K		36.5	130	131?	100
Northwood	Mob. Cel.	478	1400-2800	12Ku+8K	256K			130		100
Northwood**	P 4	478	1800-2600	12Ku+8K	512K		55	130	146-131	100
Northwood**	P 4 "B"	478	2267-2800	12Ku+8K	512K		55	130	146-131	133
Northwood**	P 4 HTT	478	3067	12Ku+8K	512K		55	130	146-131	133
Northwood**	P 4 "C"	478	2400-3400	12Ku+8K	512K		55	130	146-131	200
Gallatin**	P 4 EE	478	3200-3400	12Ku+8K	512K	2M	55+123	130	231-237?	200
Prestonia	Xeon DP	603	1600-3000	12Ku+8K	512K		55	130		100	1-2
Prestonia	Xeon DP	604	2000-3067	12Ku+8K	512K		55	130		133	1-2
Prestonia	Xeon DP	604	3067-3200	12Ku+8K	512K	1M	55+61	130		133	1-2
Gallatin	Xeon MP	603	1500-2800	12Ku+8K	512K	1M	55+61	130		100	1-4
Gallatin**	Xeon MP	603	2000-2700	12Ku+8K	512K	2M	55+123	130	231-237?	100	1-4
Gallatin	Xeon MP	603	3000	12Ku+8K	512K	4M	55+246?	130		100	1-4
Prescott 256?	Cel D	478/775	2400-3200	12Ku+16K	256K			90		133
Prescott	P 4 "A"	478	2400-2800	12Ku+16K	1M		125	90	112	133
Prescott	P 4 "E"	478	2800-3400	12Ku+16K	1M		125	90	112	200
Prescott	P 4 "E"	T/775	2800-???	12Ku+16K	1M		125	90	112	200
Prescott	P 4 "E"	T/775	???-???	12Ku+16K	2M			90		200/266
Nocona	Xeon	T/775?	2800-3600+	12Ku+16K	1M		125	90	112?	200	1-2
Irindale						2M		90		200?
Banias	Cel M	478M	1300-1500	32K+32K	512K			130		100
Banias	P M	478M	900-1800	32K+32K	1M			130		100
Dothan	Cel M	478M	900-1500	32K+32K	1M			90		100/133
Dothan	P M	478M	1000-2400	32K+32K	2M			90		100/133
Potomac								65
Smithfield											2C
Jonah	P M?							65?			2C
Tulsa
Merom
Conroe
Gilo
Whitefield

Intel IA64 Processors
Merced****	Itanium1	PAC-418	733-800	16K+16K	96K	2-4M	25+300	180	300	66	512
McKinley+	Itanium2	PAC-611	900-1000	16K+16K	256K	1.5-3M	221	180	421	100	512
Deerfield	Itanium2	PAC-611	1000, 1500?	16K+16K	256K	1.5M?		130	266?	100	512
Madison++	Itanium2	PAC-611	1300-1500?	16K+16K	256K	2-6M	477	130	374	100	512
Fanwood	Itanium2	PAC-611	1500-1667?	16K+16K	256K	9M		130		100/166	512
Montecito	Itanium2?					24M?	1700?	90			2C?
Millington	Itanium2?
Dimona	Itanium2?										2C
Montvale	Itanium2?
Tukwila	Itanium2?										16C?
Foxton	Itanium2?
Pellston	Itanium2?
* Die Size and/or transistor count is based off a larger CPU core with a portion of the die disabled.
** Various steppings/sources listed different die sizes.
*** The bus speed on the P4, PM, CM, and Itanium is quad-pumped, but the CPU multiplier is based off the listed speed.
**** Figures for Merced based off of 4M L3 cache version.
+ Figures for McKinley based off 3M L3 cache version.
++ Figures for Madison based off 6M L3 cache version.
+++ All Itaniums are said to be 512-way SMP capable, but this is more a factor of the motherboard and system design than the chip itself (I think).

Notes on the Intel side of things are similar to the AMD side. There are again a couple cores that have an asterisk, indicating that the core was a "downgraded" version of a faster core, mostly with the Celeron processors. The double-asterisks are for chips that had varying die sizes in the various steppings. This probably occurs to a small degree in most chips, but in the Cascades, Coppermine, and Northwood cores, the changes were well documented and rather drastic. Thoroughbred A to B in AMD was only a 4 mm2 die size increase, while Coppermine fluctuated between 106 mm2 to 90 mm2, and Northwood went from 146 mm2 to 131 mm2. My guess is that it was due in part to hand-optimizing the layouts of the cores, but if anyone has precise details on the hows and whys of the decreases, I would like to hear them.

In order to make the charts fit nicely within the space constraints, x86-64 was removed from the column lists. As of now, the only Intel CPUs that are known to include x86-64 support are the Nocona and Potomac cores. There will almost certainly be more in the future. The L1 cache of the P4 chips includes a trace cache, which stores decoded micro-ops, abbreviated uops. In the chart above, the trace cache corresponds to the L1 instruction cache found in typical CPUs, and 12Ku+16K means the cache has the ability to store 12,000 micro-ops as well as a standard 16KB of L1 data cache.

You can see that Intel also has 2C (dual core) designs in their roadmap, as well as a highly speculative 16C (sixteen core!) Itanium. Whether or not Tukwila will ever see the light of day is anyone's guess - it could simply be a mythical design that some hardware sites fantasize about. Transistor count on such a chips would likely be several BILLION transistors. (On a different note, I was recently up in Tukwila, WA purchasing a mountain bike from a pawn shop. They didn't have any processors for sale, unfortunately.)

In contrast to AMD, Intel has had several major architecture revisions during the past seven or so years. AMD pretty much stuck with the K7/Athlon core for all their processors, which was admittedly a very good design. Intel, with its deeper pockets, attacked on numerous fronts. First was the Pentium III line, which more or less ended in a draw with their rival AMD. Prompted by marketing - because "clockspeed sells" - Intel came up with a radical new architecture dubbed NetBurst, the basis of the Pentium 4. NetBurst was a success on the desktop, but it really was too power hungry for laptops, so Intel decided to pursue a completely separate architecture for its mobile processors, which is now also penetrating Blade and other low voltage markets. Finally, shortly after the launch of the Athlon 64, Intel countered with their reworked NetBurst architecture and the Prescott line of processors. Add to this the long-awaited launch of IA-64 (roughly ten years in the making!) which was a completely new architecture that was even more radical than NetBurst. Intel has been busy, needless to say.

For their desktop chips, SMP was available both officially and unnofficially. The Celeron chips were not intended for SMP use and were never validated (by Intel) to work in such configurations. However, enterprising motherboard makers like Abit with their BP6 board allowed users to run early Celerons in dual CPU configurations. Intel put a stop to that with Coppermine-128 and Tualatin-256 (if you can call it that) Celerons. The P3 Xeon chips were all "multi-processor" configurations, capable of up to 8-way SMP. Such support was more dependent on the motherboard and chipset, though, so most setups topped out at 4-way SMP. Intel had a chipset that linked two 4-way buses together for their 8-way configuration, while ServerWorks created a chipset and motherboard that supported 8-way directly. In theory, they could have even followed Intel's example and linked two buses together to have a 16-way SMP setup, although at that point motherboard size becomes a difficult issue.

Itanium and SMP is a special case that needs further clarification. SMP is not always listed in the above chart, but all Itaniums are said to be capable of 512-way SMP. This is really more of a factor of the motherboard(s) and system design than the chip itself. For example, special high-end clustered systems have been built using AMD Athlon MP and Opteron CPUs as well as Xeon chips that have as many as 128 chips in a "single" system. Itanium is a similar case with SMP. Motherboards with up to eight sockets exist for Itanium, but 512-way SMP requires special hardware beyond the motherboard. (Please feel free to correct me if that's wrong, but I'm pretty sure this is the case. I can't imagine what a motherboard for 512 Itaniums would even look like if it were to exist - 8x8 feet in size?)

Update: A couple people pointed out issues with the naming of the Celeron processors. At the time, Intel used "A" to designate processors that overlapped an existing model. So there were cacheless Celeron 266/300 processors, and the 266/300 with 128K L2 cache had an "A" suffix. This occurred again with the Celeron 533, and once more with the Celeron 1000/1100. In a similar vein, the Klamath core was only 350 nm, while Deschutes was 250 nm. It was initially listed as 350/250 as there were certain Deschutes cores that were released as a pseudo-Klamath, for instance the P2 300 MHz SL2W8. There was not any way to actually tell (other that word of mouth) which P2 chips had the Klamath core and which had the Deschutes core. The chart has now been corrected by putting in a 250 nm 266-333 Deschutes line.