Intel CPU Roadmap: Less is More

Intel Server Processors

In the server and workstation segment - or "Enterprise Processors" if you prefer - Intel continues to develop both their Xeon line as well as the IA-64 based Itanium line. We'll start with the more common Xeon roadmap. We have further broken down the Xeon lineup into the uni-processor (UP), dual-processor (DP) and multi-processor (MP) segments.

Pentium 4 Xeon Lineup
Xeon Uni Processor
Processor	Speed	L2 Cache	L3 Cache	FSB	Launch Date
Xeon UP 4.0F	4.00 GHz	1 MB		800 MHz	Cancelled
P4XE 3.73	3.73 GHz	2 MB		1066 MHz	* Desktop Only
Xeon UP 3.8F	3.80 GHz	2 MB		800 MHz	Q2'05
Xeon UP 3.8F	3.80 GHz	1 MB		800 MHz	Q4'04
Xeon UP 3.6F	3.60 GHz	2 MB		800 MHz	Q1'05
Xeon UP 3.6F	3.60 GHz	1 MB		800 MHz	Already Available
Xeon UP 3.4F	3.40 GHz	2 MB		800 MHz	Q1'05
Xeon UP 3.4F	3.40 GHz	1 MB		800 MHz	Already Available
Xeon UP 3.2F	3.20 GHz	2 MB		800 MHz	Q1'05
Xeon Dual Processor
Processor	Speed	L2 Cache	L3 Cache	FSB	Launch Date
Xeon DP 3.8F	3.80 GHz	2 MB		800 MHz	Cancelled
Xeon DP >= 3.6F	>= 3.60 GHz	2 MB		800 MHz	Q3'05
Xeon DP 3.8F	3.80 GHz	1 MB		800 MHz	Q4'04
Xeon DP 3.6F	3.60 GHz	2 MB		800 MHz	Q1'05
Xeon DP 3.6F	3.60 GHz	1 MB		800 MHz	Already Available
Xeon DP 3.4F	3.40 GHz	2 MB		800 MHz	Q1'05
Xeon DP 3.4F	3.40 GHz	1 MB		800 MHz	Already Available
Xeon DP 3.2F	3.20 GHz	2 MB		800 MHz	Q1'05
Xeon DP 3.2F	3.20 GHz	1 MB		800 MHz	Already Available
Xeon DP 3.0F	3.00 GHz	2 MB		800 MHz	Q1'05
Xeon DP 3.0F	3.00 GHz	1 MB		800 MHz	Already Available
Xeon DP 2.8F	2.80 GHz	1 MB		800 MHz	Already Available
Xeon Multi Processor
Processor	Speed	L2 Cache	L3 Cache	FSB	Launch Date
Xeon MP 3.66	3.66 GHz	1 MB		667 MHz	Q1'05
Xeon MP >= 3.50	>= 3.50 GHz	1 MB	8 MB	667 MHz	Q2'05
Xeon MP >= 3.50	>= 3.50 GHz	1 MB	4 MB	667 MHz	Q2'05
Xeon MP 3.16	3.16 GHz	1 MB	4 MB	667 MHz	Q2'05
Xeon MP 3.16	3.16 GHz	1 MB		667 MHz	Q1'05
Xeon MP 3.0	3.00 GHz	512 KB	4 MB	400 MHz	Already Available
Xeon MP 2.7	2.70 GHz	512 KB	2 MB	400 MHz	Already Available
Xeon MP 2.2	2.20 GHz	512 KB	2 MB	400 MHz	Already Available
Xeon MP 2.0	2.00 GHz	512 KB	1 MB	400 MHz	Already Available

Changes in the Xeon lineup in many ways mirror what we saw on the desktop front, with Intel being even more conservative. Unlike the desktop parts, all of the Xeon chips based off the Prescott NetBurst core (i.e. Nocona, Cranford, and Potomac) have EM64T support enabled. There may still be some older pre-E-0 stepping 1MB cache cores around, but they are no longer in production.

On the UP parts, we again see the cancellation of the 4.0 GHz Nocona, while in the DP group we see the cancellation of the 3.8 GHz Irwindale. The reason for the removal of the P4XE 3.73 as a workstation part is not quite the same: the 925XE chipset does not support ECC RAM, which Intel requires for their workstation processors. The P4XE with 1066 FSB will thus be relegated to the enthusiast sector until Intel can come out with a newer chipset. A similar occurrence happened with the initial launch of the 925X chipset, as only later revisions have allowed for DDR2 to function with ECC memory.

There are once more several "greater than or equal to" entries in the roadmap, which in this case we assume to be there pending testing and validation of the parts in an enterprise environment. One thing that Intel has always prided itself on was rock solid stability in the server segment, and other than a few minor slips they tend to deliver. Intel would rather cancel parts or lower clock speeds than risk any instability in the server market. The desire for stability over performance is also reflected in the use of the slower 400 and 667 MHz FSB on the Xeon MP parts. The 4M and 8M L3 cache Potomac cores will be available in Q2'05, but final clock speeds remain an unknown at present, with a target of somewhere around 3.5 GHz.

Itanium 2 Lineup
Itanium Dual Processor
Processor	Speed	L3 Cache	FSB	Launch Date
Itanium 2	Dual Core	TBD	667 FSB	Q4'05
Itanium 2	Dual Core	TBD	533 FSB	Q4'05
Itanium 2 1.6	1.60 GHz	3 MB	533 FSB	Q4'04
Itanium 2 1.6	1.60 GHz	3 MB	400 FSB	Already Available
Itanium 2 1.3 LV	1.30 GHz	3 MB	400 FSB	Nov '04
Itanium Multi Processor
Processor	Speed	L3 Cache	FSB	Launch Date
Itanium 2	Dual Core	TBD	667 FSB	Q4'05
Itanium 2	Dual Core	TBD	533 FSB	Q4'05
Itanium 2	TBD	9 MB	667 FSB	Q3'05
Itanium 2 1.6	1.60 GHz	9 MB	400 FSB	Nov '04
Itanium 2 1.6	1.60 GHz	6 MB	400 FSB	Nov '04
Itanium 2 1.5	1.50 GHz	4 MB	400 FSB	Nov '04

On the Itanium side of the roadmap, we again see the conservative nature of the market. 533 and 667 FSB designs have been pushed back, with the note that they are "dependent on OEM platform capability and validation." The chipsets and processors are available to Intel's partners for testing right now, but it does not look like any will be ready for public consumption just yet. The Madison 9M part that was originally supposed to launch in Q1'05 has been pushed to Q3'05 with clock speed likely to be in the 1.6 GHz range, based on information in past roadmaps. Q4'05 marks the availability of dual core Millington processors, with clock speeds again to be determined. They could very easily slip into 2006, although testing and validation of the parts will begin sometime in 2005.

Most of us may never actually see let alone use an IA-64 platform, but the technologies used in such high-end parts invariably trickle down into the mainstream processors. What sort of technologies are we talking about? One example is the redundant L3 cache design that is used in the Itanium. Due to the large die size of the chips, a flaw in the silicon matrix has a chance of drastically reducing the yields. Since the probability is high that flaws will occur in the large L3 cache rather than in the processor core itself, Intel has designed in some redundancy so that individual L3 banks can be deactivated and the work can be relocated to backup banks. With a die size that is more than four times as large as current Prescott chips, such precautions make sense. Another feature that will likely one day make it's way into desktop processors is the higher dispatch rate of the Itanium cores. Where NetBurst and K8 cores make do with a dispatch rate of up to 3 instructions per clock cycle, current Itanium 2 chips can dispatch up to 8 instructions per core per clock, and future revisions of the architecture could increase this further. It may take a while before we see these features in our home computers, but sooner or later they will come.

That wraps it up for this update of the Intel roadmap. Please remember that all of the dates and information in this roadmap is of a preliminary nature and could easily change. The cancellation of several parts in this update is clear evidence of that fact. Also, this is only a roadmap and not a comparison of processor performance, and not an endorsement per se of any of the parts. We are looking at what Intel is planning relative to what they already have available, and we'll worry about detailed comparisons with AMD when and if the parts actually launch.