Interview with AMD's Fred Weber - The Future of AMD Microprocessors
by Anand Lal Shimpi on March 31, 2005 12:00 AM EST- Posted in
- CPUs
Weber's Thoughts on Cell
Ever since its official introduction, we've been going around asking everyone we ran into about their thoughts on IBM/Sony/Toshiba's Cell microprocessor, and Fred Weber was no different. Surprisingly enough, Weber's response to the Cell question was quite similar to Justin Rattner's take on Cell. Weber saw two problems with Cell:As we concluded in our Cell investigation, the approach to microprocessor design of having one general purpose core surrounded by several smaller cores is not one that is unique to Cell. Intel has now publicly stated that this heterogeneous multi-core approach is, at a high level, something that they will be pursuing in the next decade. The problem is that to be produced on a 90nm process, the individual cores that make up Cell has to be significantly reduced in complexity, which Weber saw as an unreasonable sacrifice at the current stage.
- Cell is too far ahead of its time in terms of manufacturing, and
- Cell is a bit too heterogeneous in its programming model, referring to Cell's approach as both asymmetric and heterogeneous (we'll explain this in a bit).
The next problem that Weber touched on was the Cell approach to a heterogeneous multi-core microprocessor. To Fred Weber, a heterogeneous multi-core microprocessor is one that has a collection of cores, each one of which can execute the same code, but some can do so better than others - the decision of which to use being determined by the compiler. Weber referred to his version of heterogeneous multi-core as symmetric in this sense. Cell does not have this symmetric luxury; instead, all of their cores are not equally capable and thus, in Weber's opinion, Cell requires that the software needs to know too much about its architecture to perform well. The move to a more general purpose, symmetric yet heterogeneous array of cores would require that each core on Cell must get bigger and more complex, which directly relates back to Weber (and our) first problem with Cell that it is too far ahead of its time from a manufacturing standpoint.
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stephenbrooks - Thursday, March 31, 2005 - link
I'm a bit confused by the terminology in places. Doesn't ILP mean "Instruction-Level Parallelism", i.e. that applies to distributing instructions between different execution units, and perhaps other tricks like out-of-order execution, branch prediction etc. But it certainly does NOT include "frequency", as seems to be implied by the first page! Unless it means that the longer pipeline will be interpreted as more parallelism (which is true). But that's not the only way to increase clock speed... a lot comes from the process technology itself.MrEMan - Thursday, March 31, 2005 - link
I just realized that the link to "IDF Spring 2005 - Predicting Future CPU Architecture Trends" requires that you go to the next page, and not the one the link points to, and it is there where ILP/TLP is explained.MrEMan - Thursday, March 31, 2005 - link
What exactly is ILP/TLP ?sphinx - Thursday, March 31, 2005 - link
#12 PeteRoyI would have to agree with you.
Son of a N00b - Thursday, March 31, 2005 - link
Great article Anand! I feel better informed and this was something that filled up my little spot of curiosity I had saved for the future of processors.It seems as if AMD will continue to keep up the great work. I will be a customer for a long time.
hectorsm - Thursday, March 31, 2005 - link
blckgrffn I did not see your post until now. Your explanation seem to make a lot of sense. I guess is now a matter of opinion to how much is "30%" worth in terms of heat and transistor.thanks.
hectorsm - Thursday, March 31, 2005 - link
Thanks Filibuster. The article confirms the up to 30% gain in processing power under certain multithreaded scenarios. But I am still confused to why this is a waste of resources specially when HT was design for multiple thread use.blckgrffn - Thursday, March 31, 2005 - link
The point of hyperthreading being a waste of resources is that it costs A LOT to put features like that into hardware, and the die space and tranistors used to do HT could probably have been used in better way to create a more consistent performance gain, or could have been left out all together, reducing the complexity, size, power use/heat output of the processor and putting a little bit more profit per chip sold at the same price into Intels pocket. That is why it is a misuse of resources.Nat
BLHealthy4life - Thursday, March 31, 2005 - link
Just release the FX57 already...hectorsm - Thursday, March 31, 2005 - link
"not sure what you mean by "processing efficiency". all HT does is virtually separate the processor into two threads. maybe I'm missing something, but I can't figure out why everyone associates HT with performance gain. "There are supposedly fewer misprediction in the pipeline since there are two threads sharing the same pipes. Even when the total processing power is cut in halth, the sum of the two appears to be greater with HT. It has been reported up to 30% increase in total output when running two intances of folding@home and HT.
So I am still wondering why Fred is calling it a "misuse of resources". Maybe he knows something we don't. It would be interesting to know more about this. Maybe someone at AnandTech get get a clarification from Fred?