AMD’s 90nm Athlon 64s have been almost everything that the enthusiast community has wanted them to be. Being little more than a die shrink, the 90nm chips are cooler, can run faster, and are cheaper to make than their 130nm counterparts. But the improvements didn’t stop with the move to 90nm. More recently, AMD has released their Revision E 90nm Athlon 64 cores, which featured a number of small improvements.

One of the biggest improvements to Rev E on paper was the added support for SSE3 instructions, originally introduced on Intel’s 90nm Prescott based Pentium 4. When the Rev E cores had first arrived on the scene, we took a look at the performance improvements offered by SSE3 support and came up empty handed .

There were a number of other improvements made to the Rev E core, including an updated memory controller - boasting support for mismatched DIMM sizes per channel, improved memory access performance for integrated graphics cores and a few other performance tweaks that AMD hasn’t gone into much detail about.

One such barely mentioned improvement was support for a handful of new memory dividers. With an on-die memory controller, AMD has to be particularly careful about adopting new memory technologies, as the wrong choice could leave them with a bunch of CPUs that are basically un-sellable. Over a year ago, AMD had been talking about bringing support for faster than DDR400 speeds to the Athlon 64 - assuming JEDEC would ratify the specifications. AMD waited until the very latest possible moment to decide on whether DDR2 or a faster DDR1 memory controller would be in their future, which is why it took them until just a few months ago to really start talking about DDR2 support. Potentially as a backup plan, the Rev E chips include unofficial support for memory faster than DDR400, without overclocking the Hyper Transport bus.

AMD obviously didn’t speak much about support for these higher speed DRAM options, mainly because they are not official specs, and thus, AMD doesn’t officially support them. But, the fact of the matter is that many folks have faster-than-DDR400 memory, and the new Rev E CPUs can now take advantage of that.

The New Memory Speeds
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  • wien - Monday, July 11, 2005 - link

    #15: It's not like they will stop making s939 CPUs the instant they launch M2. You'll be fine for a couple of years for sure.
  • PrinceGaz - Monday, July 11, 2005 - link

    #13- Lots of mobos support 3.3V RAM voltage. Only problem is they take PC66/100/133 modules rather tahn DDR :)
  • AnnihilatorX - Monday, July 11, 2005 - link

    Well in the end AMD still planned to move to DDR2
    To me they said S939 would last long
    But they are moving to socket M2 and DDR2 next year

    It would have been much better if they stick to s939 and wait for DDR3 instead

    #12 I think it's next year
  • Viditor - Monday, July 11, 2005 - link

    "According to [H] it is the San Diego core which has the improved (fixed) memory controller (see quote below). So do you have to be careful to get San Diego or is Venice ok?"

    San Diego, Venice, DC Opterons, and the X2 all have the improved memory controllers...
  • elecrzy - Monday, July 11, 2005 - link

    #11: how many mobo's do you know support 3.3V+ RAM voltage and how many RAM sticks to you know support DDR500 with 2225 timing?
  • bupkus - Monday, July 11, 2005 - link

    When does AMD's roadmap start using DDR2?
  • JustAnAverageGuy - Monday, July 11, 2005 - link

    A64s aren't bandwidth starved. We knew that much already :)

    When you crank up the HT\FSB speeds you're normalyl trying to get the CPU clock speed up. Dividers just help if the memory can't keep up. :)
    What's with all the OCZ+DFI love going on around here anyway? :)
  • GTMan - Monday, July 11, 2005 - link

    According to [H] it is the San Diego core which has the improved (fixed) memory controller (see quote below). So do you have to be careful to get San Diego or is Venice ok?

    "The San Diego core brings with it some very important things. Primarily, it has what AMD terms as a “more flexible memory controller.” We at HardOCP would prefer to call it a “fixed memory controller.” “Fixed” as in the older one was broken."

    http://www.hardocp.com/article.html?art=Nzg3
  • creathir - Monday, July 11, 2005 - link

    Well, I for one am just GLAD Anand is not dead... was begining to wonder... Maybe you got invited up to Redmond for a little chat due to you article that got pulled? At least you're alive and the M$ob did not get ya...
    Great work on the article. I suppose as long as I do not play BF2 on one screen while rendering a scene in 3DStudioMax on another, I should be fine.
    - Creathir
  • Joepublic2 - Monday, July 11, 2005 - link

    "i remember when ddr400 wasn't official..."

    I do too, DDR333 was intended to be the last speed grade of DDR. Samsung and other memory makers had good yields of DDR400, and were having big problems with DDR2. Those have been fixed, and DDR2 is ready to go, having recently become even less expensive that DDR.

    http://www.xbitlabs.com/news/memory/display/200507...

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