Athlon 64 Revision E: Unofficial DDR500 Support

The New Memory Speeds

There are a total of four new memory dividers unofficially supported by the Rev E Athlon 64s, but not all of them can be used by everyone. In order to understand why, you have to understand a bit about how memory speed is calculated by the Athlon 64's on-die memory controller.

In a Pentium 4 system, the memory controller is located on the chipset, and derives its clock from the FSB frequency of the CPU through the use of a FSB:DRAM clock ratio. For example, with a 1:1 clock ratio, a 200MHz FSB clock would result in a 200MHz DRAM clock.

The Athlon 64 is a bit different, since it does not have a conventional FSB. So, instead of the memory clock being determined by a ratio of the FSB clock, it is determined by a few factors.

The basic equation is this:

DRAM Clock = CPU Clock / (ceil(CPU Clock Multiplier/Memory Divider))

Most of the elements of the equation are pretty obvious; the DRAM clock is the resulting memory frequency. Note that this is your non-DDR memory frequency. For example, if the DRAM Clock is 200MHz, we're talking about DDR400; if it is 166MHz, then we're talking about DDR333.

The CPU Clock is the final CPU clock of your processor, which is made up of two components: the Hyper Transport clock and your currently selected clock multiplier. The HT clock is 200MHz by default, but can obviously be overclcoked. The CPU Clock Multiplier is set at the factory, but lower multipliers are unlocked for Athlon 64s, while all multipliers are unlocked for FX processors.

The Memory Divider is a ratio supported by the CPU's memory controller, and it is this set of ratios that has been expanded in the Rev E memory controller.

Finally, there's this "ceil()" function. The ceil() function is a pretty basic mathematical function that returns the smallest integer value greater than or equal to its argument (the number passed to the function in the parentheses). For example, ceil(5.5) = 6, and ceil(10.1) = 11. Pretty simple, right?

So, you plug in all of the variables of that equation, and solve, and you get your final DRAM clock.

You'll notice one very important thing about this equation: the DRAM clock is dependent on the Athlon 64's clock speed , which means that in order to achieve the same memory speed on all processors with differing clock speeds, the memory divider is going to have to, well, vary.

Prior to the Rev E CPUs, the Athlon 64's memory controller supported enough dividers to allow for DDR400 to be supported at all clock speeds; from 1.8GHz all the way up to the present-peak of 2.8GHz on the Athlon 64 FX-57. The Rev E CPUs support those same dividers, but add the following:

13/12, 7/6, 5/4 and 4/3

If you plug these ratios into the equation above, you can come up with a list of the new memory speeds unofficially supported by Rev E CPUs:

CPU	Clock Speed	Memory Dividers
		13/12	7/6	5/4	4/3
AMD Athlon 64 FX-57	2.8GHz	215MHz	233MHz	233MHz	255MHz
AMD Athlon 64 3800+	2.4GHz	200MHz	218MHz	240MHz	266MHz
AMD Athlon 64 3500+	2.2GHz	200MHz	220MHz	244MHz	244MHz
AMD Athlon 64 3200+	2.0GHz	200MHz	222MHz	250MHz	250MHz
AMD Athlon 64 X2 4800/4600+	2.4GHz	200MHz	218MHz	240MHz	266MHz
AMD Athlon 64 4200/4400+	2.2GHz	200MHz	220MHz	244MHz	244MHz

The above table is comprised of all of the Socket-939 Venice (90nm Rev E) cores currently on the market, as well as the Athlon 64 X2 processors, which also support the new dividers.

You'll notice that not all of the dividers are useful, some resulting in the same old 200MHz DDR400 memory clocks while others offering duplicate speeds (e.g. the 7/6 and 5/4 dividers with the FX-57).

But at the same time, a number of them produce some very interesting, and potentially useful memory configurations without ever overclocking your CPU or the Hyper Transport bus. For example, at 233MHz, the Athlon 64 FX-57 can now run with unofficial DDR466 memory. And at 250MHz, the Athlon 64 3200+ can use DDR500 memory.

At DDR466, you get approximately 15% more memory bandwidth over a standard dual channel DDR400 configuration with an Athlon 64. At DDR500, you get a full 25% increase in memory bandwidth.

Historically, the Athlon 64 hasn't really been memory bandwidth bound, since the move to Socket-939, which gave it a full 128-bit wide memory bus, and more bandwidth than these CPUs could use.

With the move to dual core however, the effective memory bandwidth that each core gets is significantly reduced, as they both have to share the same 128-bit wide memory interface normally dedicated to a single processor. So in theory, the new dual core X2 line of processors could be a good candidate for these new memory dividers.

The other situation where higher clocked memory is important is with higher clock speed CPUs. The faster that your CPU clock gets, the quicker it can process data and thus, the faster that it needs information and the more memory bandwidth that it needs.

The lower clocked CPUs are less likely to see any real performance difference, with DDR400 being more than sufficient for their needs.