Intel Q3'05 Roadmap: Conroe Appears, Speculation Ensues
by Kristopher Kubicki & Jarred Walton on August 8, 2005 3:13 AM EST- Posted in
- CPUs
Intel CPU Roadmap Update
We have a small update to the Intel desktop roadmap, and not much has really changed. Everything from our last update remains the same, and it's basically business as usual. So what's new? We'll start off with the most interesting area in our view, the dual core units. As usual, we'll highlight the updates and additions.
| Intel Desktop Performance Roadmap | ||||
| Processor | Core Name | Clock Speed | Socket | Launch Date |
| ??? | Conroe | ??? | ??? | 2H'06 |
| Pentium D >= 950 | Presler | ??? | LGA 775 | Q2'06 |
| Pentium D 950 | Presler | 3.4 2x2MB | LGA 775 | Q1'06 |
| Pentium D 940 | Presler | 3.2 2x2MB | LGA 775 | Q1'06 |
| Pentium D 930 | Presler | 3.0 2x2MB | LGA 775 | Q1'06 |
| Pentium D 920 | Presler | 2.8 2x2MB | LGA 775 | Q1'06 |
We already covered the arrival of the Presler Pentium D cores last month (and Smithfield has been available for a few months). The chips will be dual core 65nm parts with EM64T, VT, EIST, and XD. If you're not familiar with those acronyms, here's the recap:
- EM64T adds 64-bit support and is the Intel equivalent of AMD64.
- XD provides some protection against buffer overflow attacks, again matching up to AMD's NX (No-eXecute) technology.
- VT stands for Virtualization Technology and provides hardware level support for running multiple OSes concurrently on a single computer.
As we mentioned in our recent AMD roadmap update, it was only possible to run multiple OSes concurrenty in the past through such third party tools as VMware, and the hardware support should increase the performance quite a bit. As with the other technologies mentioned, VT has an AMD counterpart, dubbed Pacifica. The remaining technology warrants further explanation.
EIST stands for Enhanced Intel Speedstep Technology, which allows the processors to throttle down to lower clock speeds and voltages when idle and thus conserve power. The version of EIST in the Presler core should be superior to that of the Smithfield core as it will also be available on the 2.8 GHz model. Current EIST on Pentium and Pentium D chips reduces the clock speed to 2.8 GHz, making it a useless feature for a chip that runs at 2.8 GHz by default. We don't have any specific details on the new EIST, but we hope that it will offer more benefits than a static clock speed and voltage reduction. Ideally, we'd like to see something like AMD's Cool and Quiet where all lower CPU multipliers are unlocked - that's what Intel has in their Pentium M chips as well. Overclockers in particular like to have such control; however, Intel may or may not offer that degree of tuning.
We have one new entry for a potentially faster Presler model: 960 running at 3.6 GHz is the most probable candidate, although whether or not Intel decides to release such a chip will depend on a variety of factors. The more interesting addition is Conroe, which will use Intel's next generation architecture. Details on what Conroe will bring to the table are scarce, but we would imagine that all the previously mentioned technologies will be present. The major change is that Conroe will not use the NetBurst architecture that has been used in the Pentium 4 (and derivatives) line.
For those that don't follow processors closely, here's a brief explanation on why this decision was made. The long pipeline of NetBurst has become a liability with clock speeds beyond 4 GHz producing a lot of heat. Increasing clock speeds have always created more heat, but now we're hitting the point where they begin to scale out of control. Rather than trying to find ways of dealing with 150W power levels (or perhaps even higher), Intel has designed a new architecture "from the ground up." Of course, they're not really starting over, as they'll be using elements of all of their previous designs, but Conroe will be enough of a change that it will have a new name.
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IntelUser2000 - Thursday, August 18, 2005 - link
And can u tell me how that's not significant?? Yonah isn't like Smithfield's slap-on dual core, because it has arbitration logic to manage data between two cores. And even compared to A64 dual core, its not just dual core + SRQ-like, it has bunch of other enhancements which strengthen the weakness(FPU/SSE).
To: nserra
HT takes less than 5% die size, of course IMC is good, but Pentium 4 can have IMC too. I think HT and IMC is good in their own different ways.
Cache consumes low power, and takes little die space compared to number of transistors used. If you take 4 core on Athlon64 today on the 90nm, Prescott will look cool running compared to it.
The 6MB cache in Itanium 2 takes 60% die size but only 30% power consumption.
nserra - Friday, August 19, 2005 - link
I agree IntelUser2000, but even so, if each core used c&q with some disable core capability, would be in the 30W per core range (120W total) right on track with prescott 2M and Pentium D.I don’t know if you noticed, but amd added more power to their designs while their processor are consuming less.... that must be because:
Good reasons first:
-amd will achieve higher clock speeds 3.4 GHz and up
-amd is already thinking in 4 cores processors
Bad reasons:
-amd will come with some bad 65nm tech
-or will come with some bad core (M2 with rev.F prescott like)
coldpower27 - Saturday, August 13, 2005 - link
Yeh, from current rumors Yonah is having every check box feature besides EM64T :)Like I have said I can't wait till Intel brings Conroe technology, as I always have like going the Intel route, but I don't want to go for NetBurst based processors.
45nm generation looks to be quite the change for Intel, as they are moving to those tri-gate trasistors, High K, and FD-SOI, tohugh I beleive it would be introduced at the end of 2007 rather then mid at the earliest, Conroe is expected to debut on 65nm technology, hopefully it doens't need to get an optical shrink to get good like NetBurst did and is good from the get go, like Athlon 64 was.
IntelUser2000 - Friday, August 12, 2005 - link
I heard due to the limits of the Trace Cache throughput, it only can achieve IPC of 2, not 3, so even in theory, Pentium 4 only reaches IPC of 2.About the Hyperthreading technology, I sort of disagree. If the design of the microprocessor is made to accomodate such multi-threading technology, they don't need to put 24% increase in die size like Power 5 did. I heard only with 5% increase in die size, Alpha EV8 was supposed to have performance increase of 2x, which happens to be greater than by putting another core!!!
Pentium 4's HT takes LESS than 5% die size.
nserra - Wednesday, August 17, 2005 - link
Well if you think that the 5% die for HT is very well spent, what about the 5% of the AMD Athlon64 on the integrated memory controller.JarredWalton - Saturday, August 13, 2005 - link
In practice, I'd guess that NetBurst averages an IPC of around 1.3 overall. I'd say Athlon 64 is closer to 2.0. Obviously just a guess, but when you consider how a 2.4 GHz A64 3800+ compares to the P4 3.6 (570), that seems about right. Heck, P4 might even be 1.1 to 1.2 IPC on average if K8 is 2.0. Branch misses kill IPC throughput on NetBurst, for example.We also don't know precisely (well, I don't) what the various traces represent. It could be that many traces actually take up two of the "issue slots", as traces don't have to be a single micro-op.
HyperThreading in NetBurst is really pretty simplistic. It also doens't really help improvement much except in very specific circumstances. I can't imagine any SMT configuration actually providing a bigger boost than SMP, though. (Otherwise everyone would already be doing it, rather than just NetBurst and high-end Server chips.) I seriously doubt that a 5% die space increase would be able to get more than a 10% performance increase. 10% I could see being 20 to 30%, and 15% could be 50% or more - of course, all just guesses and all under specific tests.
If you're not running multiple CPU-intensive threads, any form of SMT helps as much as SMP, which is to say not at all. Basically, this is all just guessing right now anyway, so there's no point in worrying about it too much. I have to think that Intel can get MUCH better performance with the next architecture than anything they've currently got, though. 2MB+ cache on CPUs is a lot of wasted space that could be better utilized, IMO.
nserra - Wednesday, August 17, 2005 - link
Yeah I completely agree!!
I was hoping AMD would release a 4 core processor with 128KB L2 cache for each core. That would give almost the same transistor count of 2 cores with 1MB L2. But “a lot” more speed.
Of course in MARKETING, having a processor with a total of 512KB L2 cache would be a budget one, but for me a excellent efficient design.
IntelUser2000 - Tuesday, August 16, 2005 - link
Well, a point to make is this: because the designers of Alpha CPUs managed beat every other CPU at every generation and every process generation, having simpler core, then its likely that the future generation would have done so too.Its not that companies are not using SMT because they don't know the benefits of SMT, its that they don't know how to make it good. Did you think it made sense for Intel do make Prescott core? IBM looks like best doing at SMT because they are only one of the two that actually uses SMT nowadays, the other being Intel at desktop chips. Plus, server chip design are usually pushed to their technical limits, while desktop chips are made for mainly mass production and profit.
(Exception is Itanium code-name Montecito's multi-threading, since it uses different form of it)
IntelUser2000 - Tuesday, August 16, 2005 - link
About the IPC, in theory P4 can output IPC of 2 and Athlon 64, three. So even with same branch misses, in theory Pentium 4 will be slower than Athlon 64, not to mention on the real one, it adds branch misses.About SMT, look here: http://www.realworldtech.com/page.cfm?ArticleID=RW...">http://www.realworldtech.com/page.cfm?ArticleID=RW...
"The enormous potential of SMT is shown by the expectation that it can approximately double the instruction throughput of an already impressive monster like the EV8 at the cost of only about 6% extra die area over a single threaded version of the design. That is a bigger speedup than can be typically achieved by duplicating the entire MPU as done in a 2 way SMP system!"
Though it looks as P4's multi-threading is a simple one not destined to take advantage of the architecture, its more the other way around.
Pentium 4 with limited IPC throughput(2 max), limited number of registers(8 and 16 in 64-bit), limited bandwidth, is crippling HT's ability.
Alpha EV8 was supposed to have IPC of 8 in theory, 1024 registers(!!), integrated memory controller with 20GB/sec bandwidth per CPU, and the architecture that was developed to take advantage of SMT from the beginning shows its full benefits.
Next-gen Itanium with multi-threading is a different story. Montecito doesn't use SMT, it uses different form of multi-threading, so its not really comparable.
Horshu - Friday, August 12, 2005 - link
Does Conroe's roadmap intersect early on with the 45 nm process (2007)? That was the point at which Intel was supposed to migrate over to the new high-K/metal transistor gates, although I recall something about those plans being dropped while Intel works on a new high-K process. The new gates were supposed to dramatically reduce heat dissipitation, although I have no idea what to expect from the new high-K they are working on.