Apple Makes the Switch: iMac G5 vs. iMac Core Duo

Next up, we'll look at floating point performance.

Flops, programmed by Al Aburto, is a very floating-point intensive benchmark. Analyses show that this benchmark contains:

70% floating point instructions;
only 4% branches; and
Only 34% of instructions are memory instructions.

Note that some of those 70% FP instructions are also memory instructions. Benchmarking with Flops is not real world, but isolates the FPU power.

Al Aburto, about Flops:

" Flops.c is a 'C' program which attempts to estimate your systems floating-point 'MFLOPS' rating for the FADD, FSUB, FMUL, and FDIV operations based on specific 'instruction mixes' (see table below). The program provides an estimate of PEAK MFLOPS performance by making maximal use of register variables with minimal interaction with main memory. The execution loops are all small so that they will fit in any cache."

Flops shows the maximum double precision power that the core has, by making sure that the program fits in the L1-cache. Flops consists of 8 tests, and each test has a different, but well known instruction mix. The most frequently used instructions are FADD (addition), FSUB (subtraction) and FMUL (multiplication).

MOD	FADD	FSUB	FMUL	FDIV	iMac G5 1.9GHz	iMac Core Duo 1.83GHz
1	50%	0%	43%	7%	705	876
2	43%	29%	14%	14%	490	366
3	35%	12%	53%	0%	2213	1216
4	47%	0%	53%	0%	1349	1178
5	45%	0%	52%	3%	868	1109
6	45%	0%	55%	0%	1509	1291
7	25%	25%	25%	25%	341	235
8	43%	0%	57%	0%	1440	1264
Average:					1114	942

One of the G5's strengths is in its floating point performance, and here, we see an example of that as it holds a 18% performance advantage over the Core Duo.  This does complicate the performance scene, as the move to Core Duo isn't necessarily going to be a clean victory for Apple today.

The last architectural performance test was the Queens benchmark, which does a great job of measuring the performance of a CPU's branch predictor. 

To test the branch prediction, we used the benchmark "Queens". Queens is a very well known problem where you have to place n chess Queens on an n x n board. The catch is that no single Queen must be able to attack the other. The exhaustive search strategy for finding a solution to placing the Queens on a chess board so that they don't attack each other is the algorithm behind this benchmark, and it contains some very branch intensive code.

Queens has about:

23% branches
45% memory instructions
No FP operations

On a PIII, the Branch misprediction rate is up to 19%! (Typical: 9%) Queens runs perfectly in the L1-cache.

As Johan mentioned in his article, it seemed as if a good branch predictor was very important to the chip's designers.  The necessity for a good branch predictor is also evident when you look at how long it takes the G5 to access main memory.  For this test, we looked at Queens performance with 16 queens on the chessboard:

The G5 completely dominates the Core Duo here. With a relatively short pipeline, not as much attention is usually paid to branch prediction as on a chip with a longer pipe.