PCI Express: Interconnect of the future

The PCI Express Architecture is specified in layers, which helps ease cross-platform design.

At the very bottom is the physical layer. The most basic PCI Express link consists of two low voltage differential signals: transmit and receive. A data clock is embedded using the 8/10b encoding scheme to achieve very high data rates. The initial frequency is 2.5Gb/s in each direction, with speeds expected to increase with advances in silicon technology up to possibly around 10Gb/s in each direction.

Transmit and receive signal pairs
One of the most exciting features for all the speed freaks out there is PCI Express's ability to scale speeds by aggregating links to form multiple lanes. The physical layer supports X1, X2, X4, X8, X12, X16 and X32 lane widths. Transmission over multiple lanes is transparent to other layers.



The data link layer ensures reliability and data integrity for every packet sent across a PCI Express link. Along with a sequence number and CRC, a credit-based, flow control protocol guarantees that packets are transmitted when a buffer is available to receive the packet at the other end. Packet retries are eliminated resulting in a more efficient use of bus bandwidth. Any corrupted packets are automatically retried.

The transaction layer creates request packets from the software layer to the link layer, implemented as split transactions. Each packet is uniquely identified, supporting 32-bit memory addressing as well as extended 64-bit addressing. Additional attributes including "no-snoop", "relaxed ordering" and priority are used for routing and quality of service.

Furthermore, the transaction layer comprises of four address spaces: memory, I/O, configuration (these three are already in the PCI specification) and the new Message Space. This fourth address space is used to replace prior side-band signals in the PCI 2.2 specification and does away with all the "special cycles" in the old format. These include interrupts, power management requests and resets.

Finally, the software layer is touted as of utmost importance as the key to maintaining software compatibility. The initialisation and runtimes are unchanged from PCI with the purpose of allowing operating systems to boot with PCI Express without modification. Devices are enumerated such that the operating system can discover the devices and allocate resources as necessary while the runtime again reuses the PCI load-store, shared-memory model. Whether or not modification is really required remains to be seen as "PCI Express support" is counted as one of the features of Microsoft's next Operating System codenamed Longhorn; a tacit implication that previous operating systems may not support PCI Express.