AMD Athlon

EV6 & the Athlon's Busses

We discussed earlier that although the Athlon's Slot-A connector was physically similar to the Pentium III's Slot-1 connector, the processors are not interchangeable. The reason behind this is that the two processors operate on different system, or front side, busses. The front side bus (FSB) is the connection between the CPU and the chipset, and the bus Intel has been using with the Pentium II/III, Xeon and Celeron processors is known as the GTL+ bus. GTL+ operates at 100MHz and thus provides 800MB/s of bandwidth (64-bits x 100MHz = 6400 Mb/s / 8 = 800MB/s). Intel is pushing to increase the FSB specification of GTL+ to 133MHz later this year with the Camino chipset, which would increase the available bandwidth between the CPU and chipset to a little over 1GB/s of bandwidth. For a single processor system, saturating the 800MB/s of bandwidth doesn't occur too often when you consider that a large percentage of users still only use their computers for word processing and web surfing.

Saturation of the 100MHz GTL+ bus happens most frequently in high-end workstations and servers, and is especially easy to point out in multiprocessor systems. The GTL+ bus is a shared bus, meaning that regardless of how many processors you have present in your system, they must all share the same 800MB/s of bandwidth. This is part of the reason that adding more than two processors to an Intel Xeon server begins to give you diminishing returns, and it is also part of the reason that many companies pursue multiple dual processor servers versus a handful of quad processor servers. Intel's GTL+ Shared Bus (right)

Take a single Intel Pentium III Xeon for example, there is 800MB/s of bandwidth available for use with the current GTL+ bus. Adding a second processor into the system cuts the bandwidth available per processor down to 400MB/s. Adding two more processors leaves each CPU with 200MB/s of available bandwidth between the CPUs and the chipset. See the problem?

AMD chose a different approach, rather than attempt to license GTL+ for use with the Athlon, AMD went around Intel and straight to Digital, the manufacturers of the powerful Alpha processor. Using Digital's EV6 bus protocol, AMD was able to give the Athlon a much greater potential for growth. On the transfer side of things, EV6 allows for 64-byte burst data transfers versus the 32-byte burst data transfers supported by GTL+. Translation? The EV6 is inherently capable of sending more data at a time through the bus than GTL+. The EV6 bus also adds the security of 8-bit ECC to all data transfers, a feature already implemented by Intel in the GTL+ bus but absent from all Super7 platforms.

The big difference between EV6 and GTL+ in the minds of those that first hear about it seems to be the operating frequency of EV6. The beauty of EV6 is that it takes advantage of the same technology that is behind the accelerated graphics port, or AGP in that it allows data to be transferred on both the rising and falling edges of the clock. This allows the memory bus to operate at 100MHz while delivering 200MHz (1.6GB/s of bandwidth) between the chipset and CPU because it delivers twice as much information, by transferring data on both the rising and falling edges of the clock. This allows for 1.6GB/s of bandwidth available for a single Athlon processor, but that's not where the beauty of EV6 ends.