Rambus DRAM Part 2: Performance

We were just comparing DDR SDRAM to the i820 + PC800 RDRAM combination, but the reality of the situation is that it won't be pitted against that platform and if it is, DDR SDRAM will most likely come out on top provided that the memory controller is designed properly.  The reason we can make that assumption is because, if we take the BX/PC100 performance graph and increase its peak memory bandwidth, we can essentially estimate what PC1600 DDR SDRAM (100MHz x 2) would do if it were using a memory controller like the one found in Intel's BX chipset.  Considering that PC2100 DDR SDRAM (133MHz x 2) should also become available, we can predict a lower latency and thus a lower graph indicating better overall performance than the i820 + RDRAM setup. 

The real question is, how will it stack up to dual channel PC800 RDRAM since that is what Willamette's Tehama chipset will use, and the only current implementation we have to go by is that of the i840 chipset. 

The i840 chipset is actually a bit more advanced than the i820 chipset in that it does help to reduce the latency of RDRAM at low bandwidth usage situations, not by adding a second RDRAM channel (that only increases the peak bandwidth); however we'll save the i840 versus i820 comparison for another review. 

The main thing to realize here is that PC1600 DDR SDRAM will offer a similar if not lower latency than PC800 RDRAM across the board and PC2100 DDR SDRAM should offer an even higher level of performance because of an even lower latency across the board.

We have known this from the start, the only problem with DDR SDRAM is that, because of its higher pin count than RDRAM, creating a two channel DDR SDRAM memory interface would be quite difficult and costly, which rests the fate of SDRAM on the ability for Quad Data Rate (QDR) technology to take off or a potentially higher bandwidth DDR-II standard.