SiS 645: Pentium 4 DDR - Take II

MuTIOL & The South Bridge

The 645 North Bridge uses SiS' MuTIOL interconnect to interface with the 961 South Bridge. This bus operates at 66MHz and is double-pumped meaning that it transfers data twice (and addresses once) per clock cycle. The bus is 16-bits wide and is bi-directional, allowing for 266MB/s of data to be transferred in each direction for a total of 533MB/s of bandwidth between the North and South bridges. This is twice what Intel's 850 and VIA's P4X266 offers between the two chips. Internally, the MuTIOL interconnect gets its name from the fact that there are multiple virtual channels, a total of 10 in all, that connect the individual parts of the South Bridge (for example, IDE controller, USB controllers, PCI slots, etc…) to the MuTIOL interface. These 10 virtual channels offer the same 1.2GB/s of bandwidth that the SiS 735 offered between its integrated North and South Bridges. All of this talk of peak bandwidths is mostly useless since it's very difficult to saturate the 266MB/s of bandwidth offered by Intel's Hub Architecture and VIA's V-Link interconnect much less the 533MB/s SiS' MuTIOL provides. In the future this will change, but that future is still quite a distance away.

SiS concludes that the need for more than 266MB/s of bandwidth between the North and South bridges is necessary based on the following bandwidth requirements:

While those are real peak bandwidth requirements, what isn't made clear is that it is current impossible to hit 100MB/s on any single ATA/100 drive; saturating the 133MB/s PCI bus is also very difficult without the use of a RAID card and a few hard drives; and finally USB 1.0 is 12Mbps per channel, not 12MB/s indicating each channel requires 1.5MB/s of bandwidth and not 12MB/s as SiS indicates in their 645 presentations. For a more realistic comparison, here's our take on the North/South interconnect bandwidth requirements for today's PC:

SiS will eventually offer a replacement to the 961 South Bridge in the form of the 962 which will introduce SiS' own IEEE-1394 (Firewire) controller to their Pentium 4 chipset. This IEEE-1394 controller is integrated into the single chip 745 which is due out soon. The 745 is the successor to the 735 that implements the enhanced memory controller from the SiS 645.