Roadmap Update: Pentium 4 6xx now with Enhanced Speed Step
by Kristopher Kubicki on September 1, 2004 9:57 PM EST- Posted in
- CPUs
Although we are always excited to see new processor lineups from Intel, this weeks APAC roadmap showed us the most ambitious processor rollout since Prescott.
For starters, Intel will release 4 new SKUs of Socket 775 processors based on 2MB L2 cache revisions of the Prescott core. However, the new 6xx processors are not just Prescotts with extra L2 cache slapped on them. In fact, the most interesting addition we noted with these new processors is the addition of Enhanced Speed Step Technology (EIST, also known as ESS depending on your circles). Up until now, EIST has been limited only to Pentium M processors. For those not familiar with EIST, it is simply a feature which allows a user to dynamically clock the processor during operation; very much like AMD's Cool 'n Quiet. This would certainly be a welcomed addition to the NetBurst architecture as cooling issues are more and more prevalent as Prescott ramps up.
| Intel Desktop Lineup LGA775 | ||||
| Processor | Speed | Cache | FSB | Launch Date |
| Pentium 4 XE 3.73GHz | 3.73GHz | 2MB | 1066MHz | Late Q4'04 |
| Pentium 4 XE 3.46GHz | 3.46GHz | 1MB | 1066MHz | Nov 2004 |
| Pentium 4 670 | 3.80GHz | 2MB | 800MHz | Q1'05 |
| Pentium 4 660 | 3.60GHz | 2MB | 800MHz | Q1'05 |
| Pentium 4 650 | 3.40GHz | 2MB | 800MHz | Q1'05 |
| Pentium 4 640 | 3.20GHz | 2MB | 800MHz | Q1'05 |
| Pentium 4 580J | 4.00GHz | 1MB | 800MHz | Q1'05 |
| Pentium 4 570J | 3.80GHz | 1MB | 800MHz | Q4'04 |
| Pentium 4 560J | 3.60GHz | 1MB | 800MHz | Q3'04 |
| Pentium 4550J | 3.40GHz | 1MB | 800MHz | Q3'04 |
| Pentium 4 540J | 3.20GHz | 1MB | 800MHz | Q3'04 |
| Pentium 4 530J | 3.00GHz | 1MB | 800MHz | Q3'04 |
| Pentium 4 520J | 2.80GHz | 1MB | 800MHz | Q3'04 |
Oddly, this feature which we consider one of the strongest advantages of the 6xx processor line goes completely unmentioned aside from a few footnotes in the entire roadmap. Unfortunately, one disadvantage we saw of the processor was the 800MHz front side bus. These chips are slated to launch with the 1066MHz FSB capable Glenwood/Lakeport chipsets, and that gives us little hope that we will see many 1066FSB processor launches in the near future other than Pentium 4 Extreme Edition 3.46 and 3.73. It seems the Pentium 4 720J (Pentium 4 Extreme Edition 3.73) that we mentioned in our previous roadmap update is no longer refered to as Pentium 4 720J. The Pentium 4 580 and 570 have also been pushed back a quarter.
The same cryptic "Smithfield" introduction page was found in this roadmap as well. You can check out the original we published here on AnandTech last month.
The Celeron lineup is also finally launching on the Socket 775 socket as well. The new processors, ranging from model 325 to 350, will begin deployment in a few weeks. Even though the Socket 478 Celeron roadmap continues well into Q2'05, we will only see new Celeron model releases on Socket 775; but as an added bonus all Socket 775 Celerons support the XD/NX bit. We have some future articles discussing the advantage and practicality of XD/NX and we will discuss those more in the future.
| Intel Budget Desktop Lineup LGA775 | ||||
| Processor | Speed | Cache | FSB | Launch Date |
| Celeron D 350 | 3.20GHz | 256KB | 533MHz | Q1'05 |
| Celeron D 345 | 3.06GHz | 256KB | 533MHz | Nov 2004 |
| Celeron D 340 | 2.93GHz | 256KB | 533MHz | Soon |
| Celeron D 335 | 2.80GHz | 256KB | 533MHz | Soon |
| Celeron D 330 | 2.66GHz | 256KB | 533MHz | Soon |
| Celeron D 325 | 2.53GHz | 256KB | 533MHz | Soon |
Finally, we have a few teasers about Lakeport and Glenwood. As we have mentioned in the past, Glenwood (akin to Alderwood; i925) will act as the "high" end Intel core logic. Lakeport (akin to Grantsdale; i915) will assume the lower end position. Details were skimp other than the new chipsets will both support PCIe, 7.1 channel audio, dual channel DDR2-667 and the ICH7 southbridge. 667MHz DDR2 looks extremely unambitious on Intel's behalf; particularly since we have DDR2-667 modules now and promises from SiS, ATI and VIA to deliver DDR2-800 within 6 months. Release dates for Glenwood/Lakeport stand at Q2'05.
More on XD, EIST and Pentium M later in the week!
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skiboysteve - Sunday, September 12, 2004 - link
you can even go a step further...pentium4 bus actually quad pumps data transmition so its effectivly 1066mhz (or 800 or 533 or 400) for data,
but it only double pumps address transmission, so its effectivly 533mhz (or 400 or 266 or 200) for addresses...
this stuff is all in anandtech articles from when the p4 launched.
skiboysteve - Sunday, September 12, 2004 - link
no need to worry about the p4EE, no one buys them anyway.and its a 266 internal bus x4 = 1066FSB
and you multiply the internal bus to get cpu speed.
this is like, kiddy stuff people.
IntelUser2000 - Monday, September 6, 2004 - link
I think Intel should have made regular Pentium 4's Prescott with 1MB L2 and 1066MHz bus, Pentium 4 EE should have been Prescott 2MB L2 and 1066MHz bus. There is a bigger difference between the EE and non EE then. 33% bus speed difference would do even less than current EE's advantages, although the newer EE's should have closer clock speed to the regular P4 chips.Thanks Bozo Galora for your appreciation. I usually don't get that.
KristopherKubicki: I am not sure if calling it internal bus is right. Indeed you need CPU to support the bus, but you need chipset support too. FSB description is here: http://en.wikipedia.org/wiki/Front_side_bus
Bozo Galora - Friday, September 3, 2004 - link
great post by inteluserKristopherKubicki - Thursday, September 2, 2004 - link
266 INTERNAL bus!! not front side!!Kristopher
Carfax - Thursday, September 2, 2004 - link
So for the capability to run 266FSB, they are going to charge how many hundreds of dollars more?Thats ridiculous in my opinion. Why don't they just add more cache to the P4EE (like 4MB) and make 1066FSB the standard?
Getting a 3.2E with 2MB of L2 cache and overclocking the shit out of it would be a good deal I think..
KristopherKubicki - Thursday, September 2, 2004 - link
Anemone: The multiplier is based off the internal bus. But then it gets quad pumped.Kristopher
Anemone - Thursday, September 2, 2004 - link
I'll just say now I might be wrong but wasn't 266 based, way back when, on a 33.3 bus which lends itself to 66.6, to 266.4, and thus to 1065.6? I probably just have not had enough coffee yet, but we dropped the fractions long ago, but it's from that I calculated the cpu speeds.IntelUser2000 - Thursday, September 2, 2004 - link
You are very welcome :). The link for EIST in Nocona is here: http://www.intel.com/business/bss/products/server/...The info is at the near end of the page. It's called Demand Based Switching.
Cool 'n' Quiet is much similar to Second Generation SpeedStep and PowerNow! Technology. PowerNow has like 20 steps though.
No you do not need to find P4-M info to find it has EIST, here's the link: http://support.intel.com/support/processors/mobile...
KristopherKubicki - Thursday, September 2, 2004 - link
IntelUser2000: Thanks for the post; i will look into it more. All of the processors your mentioned were P6 based which made sense to me.I have to look more into the P4-M line, i did not know it had EIST and that was not really documented in anything ive seen yet. I also have not seen anything that says EIST is on Nocona; although its a good idea it should be on all their processors.
I appreciate the info though I have sent some emails to Intel people about it.
Kristopher