AMD's Hammer Architecture - Making Sense of it All

Hammer's Caches

We've spent this entire time discussing the architecture behind the Hammer line of processors but not much attention has been given to the usual metrics we compare processors by on a higher level. The cache subsystem of the Hammer hasn't changed too much from the Athlon; the 64KB L1 data cache is 2-way set associative (low latency and thus low hit rate) as is the 64KB L1 instruction cache, both unchanged from the Athlon/Athlon XP.

The L2 cache is once again variable in size, but this time around AMD is only committing to a maximum of 1MB for the L2 cache. This is particularly interesting because upon the release of the Athlon AMD was hinting at the possibility of L2 cache sizes up to 8MB. While we do know that 1MB Athlon's based on the nixed Mustang core were produced, nothing like that ever made it to market neither did anything with a larger L2 cache.

What will most likely happen is that we will see 512KB parts for the performance desktop and entry-level workstation segments, and 1MB parts for the high end servers. On a 0.13-micron process it shouldn't be too difficult to fit 512KB on the Hammer's die and it would be a sin to outfit the processor with anything smaller especially considering AMD's stressing of its stellar performance when dealing with large workloads. If AMD were to eventually create a Duron-like version of the Hammer then it would be feasible that a processor like that would only have a 256KB L2 cache.

Once again the L2 cache is 16-way set associative like the Thunderbird/Palomino cores however AMD assured us that the L2 cache was designed independently of the Athlon making any similarities between the two purely because that's the right way for them to do it. While AMD did confirm that internally the L2 cache would be dealt with more efficiently, we have yet to get confirmation that the L2-core interface has been widened from the currently crippling 64-bit data path.